DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 221

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: BERT Bit-Error Detected (BED) Event (BBED). A latched bit that is set when a bit error is detected. The
receive BERT must be in synchronization for it to detect bit errors. Cleared when read.
Bit 5: BERT Bit-Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter
(BBC) overflows. Cleared when read and is not set again until another overflow occurs.
Bit 4: BERT Error-Counter Overflow (BECO) Event (BECO). A latched bit that is set when the 24-bit BERT error
counter (BEC) overflows. Cleared when read and is not set again until another overflow occurs.
Bit 3: BERT Receive All-Ones Condition (BRA1). A latched bit that is set when 32 consecutive 1s are received.
Allowed to be cleared once a 0 is received. This is a double interrupt bit (Section 9.6).
Bit 2: BERT Receive All-Zeros Condition (BRA0). A latched bit that is set when 32 consecutive 0s are received.
Allowed to be cleared once a 1 is received. This is a double interrupt bit (Section 9.6).
Bit 1: BERT Receive Loss-of-Synchronization Condition (BRLOS). A latched bit that is set whenever the
receive BERT begins searching for a pattern. Once synchronization is achieved, this bit remains set until read. This
is a double interrupt bit (Section 9.6).
Bit 0: BERT in Synchronization Condition (BSYNC). Set when the incoming pattern matches for 32 consecutive
bit positions. Refer to BSYNC in the TR.INFO2 register for a real-time version of this bit. This is a double interrupt
bit (Section 9.6).
—
7
0
TR.SR9
Status Register 9
26h
BBED
6
0
BBCO
5
0
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BEC0
4
0
BRA1
3
0
BRA0
2
0
BRLOS
1
0
BSYNC
0
0