DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 27

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

RSYSCLK1
RSYSCLK2
RSYSCLK3
RSYSCLK4
RMSYNC1
RMSYNC2
RMSYNC3
RMSYNC4
RCHCLK1
RCHCLK2
RCHCLK3
RCHCLK4
RFSYNC1
RFSYNC2
RFSYNC3
RFSYNC4
RCHBLK1
RCHBLK2
RCHBLK3
RCHBLK4
RSERO1
RSERO2
RSERO3
RSERO4
TBSYNC
RSYNC1
RSYNC2
RSYNC3
RSYNC4
TSERO
TCLKE
RCLK1
RCLK2
RCLK3
RCLK4
NAME
RSIG1
RSIG2
RSIG3
RSIG4
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
M10
K15
K14
K16
K10
B14
D14
A15
E14
H11
PIN
F13
W5
C6
C8
H1
N7
M8
M9
R1
C4
M3
D5
U8
K4
K9
B5
T7
K1
Y6
P3
A4
P2
B4
V7
Y2
B3
Y1
A3
V9
ETHERNET MAPPER TRANSMIT SERIAL INTERFACE
TYPE
T1/E1/J1 RECEIVE FRAMER INTERFACE
I/O
IO
O
O
O
O
O
O
O
O
I
I
Transmit Serial Data Output. Output on the rising edge of TCLKE.
Formatted to be IBO compatible.
Serial Interface Transmit Clock Input. The 8.192MHz clock reference
for TSERO, which is output on the rising edge of the clock.
Transmit Data Enable Port n (Input). An 8kHz synchronization pulse,
used to denote the first Channel 1 of the 8.192Mbps byte-interleaved IBO
data stream. Note that this input is also used to generate the transmit
byte synchronization if X.86 mode is enabled.
Receive Serial Data Output for T1/E1/J1 Transceivers 1–4. Received
NRZ serial data. Updated on the rising edges of RSYSCLK when the
receive-side elastic store is enabled. In most DS33R41 applications, all 4
RSERO outputs should be tied together and connected to RSERI.
Receive System Clock for T1/E1/J1 Transceivers 1–4. 8.192MHz
system clock. Used when the receive-side elastic-store function is
enabled. In most DS33R41 applications, all 4 RSYSCLK inputs should be
tied together and connected to RCLKI. See the Interleaved PCM Bus
Operation section for details on 8.192MHz operation using the IBO.
Receive Clock Output from the Framer on Transceiver 1. Buffered
recovered clock from Transceiver 1. Previously named RCLKO1-4. Not
used for most DS33R41 applications.
Receive Channel Block for Transceivers 1–4. A user-programmable
output that can be forced high or low during any of the 24 T1 or 32 E1
channels. Synchronous with RSYSCLK when the receive-side elastic
store is enabled. Also useful for locating individual channels in drop-and-
insert applications, for external per-channel loopback, and for per-channel
conditioning. See the Channel Blocking Registers section.
Receive Channel Clock for Transceivers 1–4. A 192kHz (T1) or
256kHz (E1) clock that pulses high during the LSB of each channel can
also be programmed to output a gated receive-bit clock for fractional
T1/E1 applications. Synchronous with RSYSCLK when the receive-side
elastic store is enabled. Useful for parallel-to-serial conversion of channel
data.
Receive Sync for Transceivers 1–4. An extracted pulse, one RSYSCLK
wide, is output at this pin, which identifies either frame (TR.IOCR1.5 = 0)
or multiframe (TR.IOCR1.5 = 1) boundaries. If set to output-frame
boundaries then via TR.IOCR1.6, RSYNC can also be set to output
double-wide pulses on signaling frames in T1 mode. If the receive-side
elastic store is enabled, then this pin can be enabled to be an input via
TR.IOCR1.4 at which a frame or multiframe boundary pulse is applied.
Receive Frame Sync (Pre Receive Elastic Store) for Transceivers
1–4. An extracted 8kHz pulse, one RSYSCLK wide, is output at this pin,
which identifies frame boundaries.
Receive Multiframe Sync for Transceivers 1–4. An extracted pulse,
one RSYSCLK wide, is output at this pin, which identifies multiframe
boundaries.
Receive Signaling Output for Transceivers 1–4. Outputs signaling bits
in a PCM format. Updated on the rising edges of RSYSCLK when the
receive-side elastic store is enabled.
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FUNCTION