DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 143

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
12.4 Arbiter Registers
The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for queuing
and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer data
to/from the SDRAM. The base address of the Arbiter register space is 0040h.
12.4.1 Arbiter Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Queue Size (RQSC[7:0]). These 7 bits of the size of receive queue associated with the
connection. Receive queue is for data arriving from the MAC to be sent to the WAN. The Queue address size is
defined in increments of 32 x 2048 bytes. The queue size is AR.RQSC1 multiplied by 32 to determine the number
of 2048 byte packets that can be stored in the queue. This queue is constructed in the external SDRAM. Note:
Queue size of 0 is not allowed and should never be set.
Bit #
Name
Default
Bits 7 to 0: Transmit Queue Size (TQSC[7:0]). This is size of transmit queue associated with the connection. The
queue address size is defined in increments of 32 packets. The range of bytes will depend on the external SDRAM
connected to the device. Transmit queue is the data queue for data arriving on the WAN that is sent to the MAC.
Note that queue size of 0 is not allowed and should never be set.
RQSC7
TQSC7
7
0
7
0
RQSC6
TQSC6
6
0
6
0
AR.RQSC1
Arbiter Receive Queue Size Connection 1
40h
AR.TQSC1
Arbiter Transmit Queue Size Connection 1
41h
RQSC5
TQSC5
5
1
5
0
RQSC4
TQSC4
143 of 335
4
1
4
0
RQSC3
TQSC3
3
1
3
0
RQSC2
TQSC2
2
1
2
0
RQSC1
TQSC1
1
0
1
1
RQSC0
TQSC0
0
1
0
1