DS33R41 Maxim Integrated Products, DS33R41 Datasheet - Page 230

• Manufacturer Part Number: DS33R41
• Description: Network Controller & Processor ICs Inverse-Multiplexing Ethernet Mapper wit
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Global Receive Signaling Reinsertion Enable (GRSRE). This bit allows the user to reinsert all signaling
channels without programming all channels through the per-channel function.
Bit 4: Receive Freeze Enable (RFE). See Section
Bit 3: Receive Force Freeze (RFF). Freezes receive-side signaling at RSIG (and RSERO if receive signaling
reinsertion is enabled); overrides receive freeze enable (RFE). See Section
Bit 2: Receive Time Slot Control for CAS Signaling (RCCS). Controls the order that signaling is placed into the
receive signaling registers. This bit should be set = 0 in T1 mode.
Bit 1: Transmit Time Slot Control for CAS Signaling (TCCS). Controls the order that signaling is transmitted
from the transmit signaling registers. This bit should be set = 0 in T1 mode.
Bit 0: Force Receive Signaling All Ones (FRSAO). In T1 mode, this bit forces all signaling data at the RSIG and
RSERO pin to all ones. This bit has no effect in E1 mode.
0 = do not reinsert all signaling
1 = reinsert all signaling
0 = no freezing of receive signaling data occurs
1 = allow freezing of receive signaling data at RSIG (and RSERO if receive signaling reinsertion is
enabled)
0 = do not force a freeze event
1 = force a freeze event
0 = signaling data is CAS format
1 = signaling data is CCS format
0 = signaling data is CAS format
1 = signaling data is CCS format
0 = normal signaling data at RSIG and RSERO
1 = force signaling data at RSIG and RSERO to all ones
GRSRE
7
0
TR.SIGCR
Signaling Control Register
40h
—
6
0
—
5
0
10.9.2.3
230 of 335
RFE
4
0
for details.
RFF
3
0
10.9.2.3
RCCS
2
0
for details.
TCCS
1
0
FRSAO
0
0