LU82551QM Intel, LU82551QM Datasheet - Page 10

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
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FIFO Subsystem Overview
The 82551QM FIFO subsystem consists of independent 3 KB transmit and receive FIFOs. Each
FIFO provides a temporary buffer for frames as they are transmitted or received. Transmit frames
queued within the transmit FIFO allow back-to-back transmission within the minimum Interframe
Spacing (IFS). The FIFOs allow the 82551QM to withstand long PCI bus latencies without losing
incoming data. Additional attributes of the FIFOs that enhance performance and functionality are:
Manageability Subsystem Overview
The 82551QM’s Manageability subsystem supports bi-directional ASF, version 1.0. In addition, it
provides a Total Cost of Ownership (TCO) interface that enables connection with alerting and
management controllers such as the Intelligent Platform Management Interface (IPMI) solutions
and Baseboard Management Controllers (BMCs).
10/100 Mbps Serial CSMA/CD Unit Overview
The 82551QM’s CSMA/CD unit allows it to be connected to a 10 or 100 Mbps Ethernet network at
half or full duplex. The CSMA/CD unit performs all of the functions of the 802.3 protocol such as
frame formatting, frame stripping, collision handling, deferral to link traffic, etc.
10/100 Mbps Physical Layer Unit
The integrated Physical Layer (PHY) unit of the 82551QM allows connection to either a 10 or
100 Mbps Ethernet network. The PHY supports Auto-Negotiation for 100BASE-TX Full Duplex,
100BASE-TX Half Duplex, 10BASE-T Full Duplex, and 10BASE-T Half Duplex. Three LED
pins indicate link status, network activity, and speed.
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Tunable transmit FIFO threshold allows elimination of underruns while concurrent transmits
are being performed.
Extended PCI zero wait state burst accesses to and from the 82551QM for both transmit and
receive FIFOs
Efficient re-transmission of data directly from the transmit FIFO when physical or data link
errors (collision detection or data underrun) are encountered, increasing performance by
eliminating the need to re-access the data from host memory
Automatic discard of incoming runt receive frames
Datasheet