LU82551QM Intel, LU82551QM Datasheet - Page 42

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
5.8.2
5.8.3
5.8.4
5.9
36
Flow Control
The 82551QM supports IEEE 802.3x frame-based flow control frames in both full duplex and half
duplex switched environments. The 82551QM flow control feature is not intended to be used in
shared media environments.
The PHY unit’s duplex and flow control enable can be selected using the NWay* Auto-Negotiation
algorithm or through the Management Data Interface.
Address Filtering Modifications
The 82551QM can be configured to ignore one bit when checking for its Individual Address (IA)
on incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the second
least significant bit of the first byte of the IA. This bit may be used, in some cases, as a priority
indication bit. When configured to do so, the 82551QM passes any frame that matches all other 47
address bits of its IA, regardless of the U/L bit value.
This configuration only affects the 82551QM specific IA and not multicast, multi-IA or broadcast
address filtering. The 82551QM does not attribute any priority to frames with this bit set, it simply
passes them to memory regardless of this bit.
VLAN Support
The 82551QM supports the VLAN standard as currently defined by the IEEE 802.1 committee. All
VLAN flows will be implemented by software. The 82551QM supports the reception of long
frames, specifically frames longer than 1518 bytes, including the CRC, if software sets the Long
Receive OK bit in the Configuration command. Otherwise, “long” frames are discarded.
Media Independent Interface (MII) Management Interface
The MII management interface allows the CPU to control the PHY unit through a control register
in the 82551QM. This allows the software driver to place the PHY in specific modes such as full
duplex, loopback, power down, etc., without the need for specific hardware pins to select the
desired mode. This structure allows the 82551QM to query the PHY unit for status of the link. This
register is the MDI Control Register and resides at offset 10h in the 82551QM CSR. (The MDI
registers are described in detail in
commands to this register and the 82551QM reads or writes the control/status parameters to the
PHY unit through the MDI register. Although the 82551QM follows the MII format, the MI bus is
not accessible on external pins.
Section 11.0, “PHY Unit
Registers”.) The CPU writes
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