LU82551QM Intel, LU82551QM Datasheet - Page 86

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
11.1.2
80
Table 42. Register 0: Control
Table 43. Register 1: Status
Register 1: Status Register
11
10
9
8
7
6:0
15
14
13
12
11
10:7
6
5
4
Bit(s)
Bit(s)
Reserved
100BASE-TX Full
Duplex
100 Mbps Half
Duplex
10 Mbps Full
Duplex
10 Mbps Half
Duplex
Reserved
Management
Frames Preamble
Suppression
Auto-Negotiation
Complete
Remote Fault
Power-Down
Reserved
Restart Auto-
Negotiation
Duplex Mode
Collision Test
Reserved
Name
Name
This bit is reserved and should be set to 0b.
1 = PHY able to perform full duplex 100BASE-TX
1 = PHY able to perform half duplex 100BASE-TX
1 = PHY able to operate at 10Mbps in full duplex
mode
1 = PHY able to operate at 10 Mbps in half duplex
mode
These bits are reserved and should be set to 0b.
0 = PHY will not accept management frames with
preamble suppressed
1 = Auto-Negotiation process completed
0 = Auto-Negotiation process has not completed
0 = No remote fault condition detected
This bit sets the PHY unit into a low power mode. In low
power mode, the PHY unit consumes no more than 30
mA.
1 = Power-Down enabled
0 = Power-Down disabled (Normal operation)
This bit is reserved and should be set to 0b.
This bit restarts the Auto-Negotiation process and is self-
clearing.
1 = Restart Auto-Negotiation process
This bit controls the duplex mode when Auto-Negotiation
is disabled. If the PHY reports that it is only able to
operate in one duplex mode, the value of this bit shall
correspond to the mode which the PHY can operate.
When the PHY is placed in Loopback mode, the behavior
of the PHY shall not be affected by the status of this bit,
bit 8.
1 = Full Duplex
0 = Half Duplex
This bit will force a collision in response to the assertion
of the transmit enable signal.
1 = Force COL
0 = Do not force COL
These bits are reserved and should be set to 0b.
Description
Description
Default
0
1
1
1
1
0
0
0
0
Default
0
0
0
0
0
0
Datasheet
RO
E
RO
RO
RO
RO
RO
RO
RO
RO
R/W
RW
RW
RW
SC
RW
RW
RW
R/W