LU82551QM Intel, LU82551QM Datasheet - Page 32

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
5.3
5.3.1
5.3.1.1
26
PCI Power Management
The 82551QM supports a larger set of wake-up packets and the capability to wake the system on a
link status change from a low power state. These added power management enhancements enable
the 82551QM to adhere to emerging standards. The 82551QM enables the host system to be in a
sleep state and remain virtually connected to the network. After a power management event or link
status change is detected, the 82551QM wakes the host system. The sections below describe these
events, the 82551QM power states, and estimated power consumption at each power state.
Power States
The 82551QM contains two sets of power management registers, one for PCI and one for CardBus,
The has one set of PCI power management registers and implements all four power states as
defined in the Power Management Network Device Class Reference Specification, Revision 1.0.
The four device power states, D0 through D3, vary from maximum power consumption at D0 to
the minimum power consumption at D3.
PCI transactions are only allowed in the D0 state, except for host accesses to the 82551QM’s PCI
configuration registers. The D1 and D2 power management states enable intermediate power
savings while providing the system wake-up capabilities. In the D3 cold state, the 82551QM can
provide wake-up capabilities only if auxiliary power is supplied. Wake-up indications from the
82551QM are provided by the Power Management Event (PME#) signal in PCI implementations
and the Card Status Change (CSTSCHG) signal in CardBus designs.
In addition to providing a host interface through the PCI bus, the 82551QM provides TCO
controller access through a dedicated System Management Bus (SMB). Additional information on
the supported TCO functionality at all power states is described in
Functionality”.
D0 Power State
As defined in the Network Device Class Reference Specification, the device is fully functional in
the D0 power state. In this state, the 82551QM receives full power and should be providing full
functionality. In the 82551QM the D0 state is partitioned into two substates, D0 Uninitialized
(D0u) and D0 Active (D0a).
D0u is the 82551QM’s initial power state following a Power-on Reset (POR) event and before the
Base Address Registers (BARs) are accessed. While in the D0u state, the 82551QM has PCI slave
functionality to support its initialization by the host and supports Wake on LAN mode.
Initialization of the CSR, Memory, or I/O Base Address Registers in the PCI Configuration space
switches the 82551QM from the D0u state to the D0a state.
In the D0a state, the 82551QM provides its full functionality and consumes nominal power. In
addition, the 82551QM supports wake on link status change
While it is active, the 82551QM requires a nominal PCI clock signal (in other words, a clock
frequency greater than 16 MHz) for proper operation. During idle time, the 82551QM supports a
PCI clock signal suspension using the Clock Run signal mechanism. The 82551QM supports a
dynamic standby mode. In this mode, the 82551QM is able to save almost as much power as it does
in the static power-down states. The transition to or from standby is done dynamically by the
82551QM and is transparent to the software.
(Section 5.3.2, “Wake-up
Section 8.0, “Manageability
Events”).
Datasheet