LU82551QM Intel, LU82551QM Datasheet - Page 29

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

Datasheet
Figure 8. Memory Write Burst Cycle
The CPU provides the 82551QM with action commands and pointers to the data buffers that reside
in host main memory. The 82551QM independently manages these structures and initiates burst
memory cycles to transfer data to and from them. The 82551QM uses the Memory Read Multiple
(MR Multiple) command for burst accesses to data buffers and the Memory Read Line (MR Line)
command for burst accesses to control structures. For all write accesses to the control structure, the
82551QM uses the Memory Write (MW) command. For write accesses to data structure, the
82551QM may use either the Memory Write or Memory Write and Invalidate (MWI) commands.
Read Accesses: The 82551QM performs block transfers from host system memory to perform
frame transmission on the serial link. In this case, the 82551QM initiates zero wait state memory
read burst cycles for these accesses. The length of a burst is bounded by the system and the
82551QM’s internal FIFO. The length of a read burst may also be bounded by the value of the
Transmit DMA Maximum Byte Count in the Configure command. The Transmit DMA Maximum
Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be
completed after an 82551QM internal arbitration.
The 82551QM, as the initiator, drives the address lines AD[31:0], the command and byte enable
lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551QM asserts IRDY# to
support zero wait state burst cycles. The target signals the 82551QM that valid data is ready to be
read by asserting the TRDY# signal.
Write Accesses: The 82551QM performs block transfers to host system memory during frame
reception. In this case, the 82551QM initiates memory write burst cycles to deposit the data,
usually without wait states. The length of a burst is bounded by the system and the 82551QM’s
internal FIFO threshold. The length of a write burst may also be bounded by the value of the
Receive DMA Maximum Byte Count in the Configure command. The Receive DMA Maximum
Byte Count value indicates the maximum number of receive DMA PCI transfers that will be
completed before the 82551QM internal arbitration.
The 82551QM, as the initiator, drives the address lines AD[31:0], the command and byte enable
lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551QM asserts IRDY# to
support zero wait state burst cycles. The 82551QM also drives valid data on AD[31:0] lines during
each data phase (from the first clock and on). The target controls the length and signals completion
of a data phase by de-assertion and assertion of TRDY#.
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
1
MW
ADDR
2
3
DATA
BE#
4
DATA
5
DATA
6
Networking Silicon — 82551QM
DATA
BE#
7
DATA
8
9
10
23