LU82551QM Intel, LU82551QM Datasheet - Page 56

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
9.1.2
50
Figure 16. PCI Command Register
Table 15. PCI Command Register Bits
Note: Bits three, five, seven, and nine are set to 0b. The table below lists the bits of the PCI Command
PCI Command Register
The 82551QM Command register at word address 04h in the PCI configuration space provides
control over the 82551QM’s ability to generate and respond to PCI cycles
register, the 82551QM is logically disconnected from the PCI bus for all accesses except
configuration accesses
register.
15:10
8
6
4
Bits
SERR# Enable
Parity Error Response
Memory Write and Invalidate Enable
Bus Master Enable
Memory Space
IO space
Reserved
SERR# Enable
Parity Error Control
Memory Write and
Invalidate Enable
Name
15
.
The format of this register is shown in the
Reserved
These bits are reserved and should be set to 0b.
This bit controls a device’s ability to enable the SERR# driver. A value of 0b
disables the SERR# driver. A value of 1b enables the SERR# driver. This
bit must be set to report address parity errors. In the 82551QM, this bit is
configurable and has a default value of 0b.
This bit controls a device’s response to parity errors. A value of 0b causes
the device to ignore any parity errors that it detects and continue normal
operation. A value of 1b causes the device to take normal action when a
parity error is detected. This bit must be set to 0b after RST# is asserted. In
the 82551QM, this bit is configurable and has a default value of 0b.
This bit controls a device’s ability to use the Memory Write and Invalidate
command. A value of 0b disables the device from using the Memory Write
and Invalidate Enable command. A value of 1b enables the device to use
the Memory Write and Invalidate command. In the 82551QM, this bit is
configurable and has a default value of 0b.
10
0
9
8
0
7
6
Description
0
5
4
Figure
0
3
16.
.
2
If a 0 is written to this
1
0
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