LU82551QM Intel, LU82551QM Datasheet - Page 79

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

10.1.13.4
10.2
Datasheet
Table 35. LAN Function Present State Register
Table 36. LAN Force Event Register
Table 37. Statistical Counters
LAN Force Event Register
The Force Event register simulates status change events for troubleshooting purposes. This register
provides the ability to simulate events by forcing values into the Function Event register.
Statistical Counters
The 82551QM provides information for network management statistics by providing on-chip
statistical counters that count a variety of events associated with both transmit and receive. The
counters are updated by the 82551QM when it completes the processing of a frame (that is, when it
has completed transmitting a frame on the link or when it has completed receiving a frame). The
Statistical Counters are reported to the software on demand by issuing the Dump Statistical
Counters command or Dump and Reset Statistical Counters command in the SCB Command Unit
Command (CUC) field.
3
2
1
0
31:16
15
14:5
4
3:0
ID
Bits
Bits
0
4
8
Transmit Good Frames
Transmit Maximum Collisions
(MAXCOL) Errors
Transmit Late Collisions
(LATECOL) Errors
Reserved
Reserved
Reserved
Reserved
Reserved
INTR
Reserved
GWAKE
Reserved
Function
Function
Counter
0b
0b
0b
0b
0
0
0
0
0
Default
Default
Bit 3 is reserved in the CardBus Specification.
Reserved.
Reserved.
Bit 0 is reserved in the CardBus Specification.
Bits [31:16] are reserved in the CardBus Specification.
This bit is used for interrupts. Writing 1b in this field will set the interrupt
bit in the LAN Function Event register. If the INTA# pin is not masked,
then it will also be activated. Writing 0b has no effect.
Bits [14:5] are reserved in the CardBus Specification.
This bit is used for general wake-up. Writing 1b in this field will set the
CSTSCHG bit in the LAN Function Event register. If the CSTSCHG pin
is not masked, then it will also be activated. Writing 0b has no effect.
Bits [3:0] are reserved in the CardBus Specification.
This counter contains the number of frames that were
transmitted properly on the link. It is updated only after the
actual transmission on the link is completed, not when the
frame was read from memory, as is done for the Transmit
Command Block status.
This counter contains the number of frames that were not
transmitted because they encountered the configured
maximum number of collisions.
This counter contains the number of frames that were not
transmitted due to an encountered collision after the
configured slot time.
Description
Description
Networking Silicon — 82551QM
Description
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