LU82551QM Intel, LU82551QM Datasheet - Page 58

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
9.1.4
9.1.5
52
Table 16. PCI Status Register Bits
PCI Revision ID Register
The Revision ID is an 8-bit read only register. The three least significant bits of the Revision ID can
be overridden by the ID and Revision ID fields in the EEPROM
Interface”). The default value of the Revision ID is 82551QM (A-step): 0Fh
PCI Class Code Register
The Class Code register is read only and is used to identify the generic function of the device and,
in some cases, specific register level programming interface. The register is broken into three byte
size fields. The upper byte is a base class code and specifies the 82551QM as a network controller,
2h. The middle byte is a subclass code and specifies the 82551QM as an Ethernet controller, 0h.
The lower byte identifies a specific register level programming interface and the 82551QM always
returns a 0h in this field.
28
27
26:25
24
23
20
19:16
Bits
Received Target Abort
Signaled Target Abort
DEVSEL# Timing
Parity Error Detected
Fast Back-to-Back
Capabilities List
Reserved
Name
This bit indicates that the master has received the target abort. This bit
must be set by the master device when its transaction is terminated by a
target abort. In the 82551QM, the initial value of the Received Target Abort
bit is 0b. This bit is set until cleared by writing a 1b.
This bit indicates whether a transaction was terminated by a target abort.
This bit must be set by the target device when it terminates a transaction
with target abort. In the 82551QM, this bit is always set to 0b.
These two bits indicate the timing of DEVSEL#:
00b - Fast
01b - Medium
10b - Slow
11b - Reserved
In the 82551QM, these bits are always set to 1b, medium.
This bit indicates whether a parity error has been detected. This bit is set to
1b when the following three conditions are met:
1. The bus agent asserted PERR# itself or observed PERR# asserted.
2. The agent setting the bit acted as the bus master for the operation in
3. The Parity Error Response bit in the command register (bit 6) is set.
In the 82551QM, the initial value of the Parity Error Detected bit is 0b. This
bit is set until cleared by writing a 1b.
This bit indicates a device’s ability to accept fast back-to-back transactions
when the transactions are not to the same agent. A value of 0b disables
fast back-to-back ability. A value of 1b enables fast back-to-back ability. In
the 82551QM, this bit is read only and is set to 1b.
This bit indicates whether the 82551QM implements a list of new
capabilities such as PCI Power Management. A value of 0b means that this
function does not implement the Capabilities List. If this bit is set to 1b, the
Cap_Ptr register provides an offset into the 82551QM PCI Configuration
space pointing to the location of the first item in the Capabilities List. This
bit is set only if the power management bit in the EEPROM is set.
These bits are reserved and should be set to 0000b.
which the error occurred.
Description
(Section 5.7, “Serial EEPROM
Datasheet