LU82551QM Intel, LU82551QM Datasheet - Page 120

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
114
Figure 35. Reference Schematic Layout (Sheet 2 of 2)
A
D
C
3 [
B /
: 1
[ E
] 0
F
R I
T
D
S
P
: 3
R
R
E
T
A
D
A
D
O
R
V
] 0
Y
M
P
Y
S
#
#
E
#
E
#
L
#
2 6
K ohm
2
0
1 .
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
C
C
C
C
N I
P
S
D I
R
G
R
C
S I
A
P
C
u
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
E
E
S
U
M
1
B /
B /
B /
B /
E
N
L
L
F
O
T
S
0
1
2
3
4
5
6
7
8
9
0 1
1 1
2 1
3 1
4 1
5 1
6 1
7 1
8 1
9 1
0 2
1 2
2 2
3 2
4 2
5 2
6 2
7 2
8 2
9 2
0 3
1 3
T
K
K
R
R
Q
T
X
E
A
E
E
E
E
E
L
#
R
R
#
_
#
R
#
A
0
1
2
3
L
G
U
#
#
T
O
E
N
P
O
#
#
C
D
_ I
100
5
1) The decoupling
capacitor should be
added to the VIO pin.
V
K ohm
2) The voltage on VIO determines the slope of the signals on the bus. Although the device
communicates if VIO is connected to 3.3V in 3.3V PCI systems, optimal performance is
acheived if this signal is connected to +5V in PCI bus systems regardless of bus voltage.
B
A
G
N
M
N
M
N
N
N
M
M
M
D
D
D
C
C
C
M
P
P
P
P
L
L
K
E
B
B
B
A
B
B
A
B
C
G
H
H
H
A
A
C
C
G
B
A
A
C
C
C
L
F
F
F
1 J
2 J
3 J
1
1
2
7
7
6
5
5
5
4
4
3
3
2
1
2
3
1
2
1
3
1
2
3
1
1
2
4
5
5
6
6
7
8
8
4
3
3
4
2
1
3
3
1
2
2
4
3
2
1
9
9
6
5
8
0
0
9
V
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
C
C
C
C
F
R I
T
D
S
P
N I
P
S
D I
R
G
R
C
S I
A
P
C
O I
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
R
R
T
A
E
E
L
M
B /
B /
B /
B /
E
E
N
S
L
L
All Vss pins are connected together on the PCB
level. The power on the symbol is broken down
between core power (Vss), local bus power (Vsspl),
transmit power (Vsst), and PCI power (Vsspp) just
for clarity.
O
D
T
S
0
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
3
3
O
K
T
K
The ISOLATE signal should be a signal that
is driven low just prior to the PCI bus shutting
down and it should be driven high immediately
following the PCI bus re-activation.
A
D
V
R
R
R
Q
T
T
E
E
E
E
E
Y
A
E
L
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
R
M
Y
S
P
R
R
#
#
R
#
#
0
1
2
3
#
#
L
A
S
#
E
#
U
E
#
#
#
#
#
#
T
T
82551QM
#
L
N
E
#
#
#
#
All Vcc pins are connected together on the PCB
level. The power on the symbol is broken down
between core power (Vcc), local bus power (Vccpl),
transmit power (Vcct), and PCI power (Vccpp) just
for clarity.
P
M
E
#
F
F
L
L
To PIIX4
F
A
F
A
F
L
/ 8
L
1
L
A
A
A /
R
O I
A
1
R
1
B
1
5
4
U
C
F
B
3
T
A I
E /
F
F
F
E /
F
F
F
X
F
H
L
A I
E /
E
L
E
V
F
F
F
F
F
F
F
F
F
L
T
L
L
L
L
F
F
F
F
F
F
F
P
L
S
E
W
E
R
E
O
X
T
R
A
A
A
L
L
L
L
L
L
L
L
L
L
L
L
L
L
C
C
E
S
E
A
L
L
1
W
D
D
C
E
C
T
1
S
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
S
E
E
S
E
X
X
I D
1
1
1
S
1
0
I T
O
R
C
O
6
K
2
1
0
Y
6
5
4
3
2
0
7
6
5
4
3
2
1
0
S
#
#
T
K
F
0
0
1
2
9
7
#
#
P
M
N
P
M
M
N
P
N
M
M
L
L
L
K
1 J
1 J
1 J
H
H
H
G
F
F
F
P
N
N
M
M
A
D
D
D
B
C
B
B
N
P
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
8
9
2
3
4
2
3
4
2
3
4
0
0
3
3
4
4
2
3
4
2
3
3
4
2
2
2
4
3
1
1
0
1
2
3
4
VREF: External VREF can be applied here if the internal reference
is not used. The internal reference is recommended, but if an
external reference is implemented, then this will cause the RBIAS
values to change.
E
E
22
C
1
1
S
p
2
F
6
649
5 2
9 1
M
3
H
V
z
S
2
2
1
B
3
3 .
K
22
p
F
E
E
E
RBIAS10 and RBIAS100
should be tuned for your
specific application. The
values shown are a
good starting value.
E
E
E
I D
D
S
O
K
3
4
2
I D
D
S
O
K
9
3
3
V
C
S
4
B
6
C
S
1
Pulldown resistors are used
on strapped pins to enable
the NAND tree test mode to
work. The value of 1 K ohm
was chosen strictly on the basis
of Intel’s test fixturing requirements
Other values can be used, but it is
recommended that resistors be used
other than hard strapping the pins.
1
K ohm
Datasheet