LU82551QM Intel, LU82551QM Datasheet - Page 103

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

12.4.2.2
12.4.2.3
Datasheet
Table 77. PCI/CardBus Timing Parameters
PCI/CardBus Timings
NOTES:
Flash/Modem Interface Timings
The 82551QM is designed to support up to 150 ns of Flash access time. The V
implementation should be connected permanently to 12 V. Thus, writing to the Flash is controlled
only by the FLWE# pin.
Table 78
illustrated in
Modem is supported through the Flash interface when the following conditions apply:
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
1. Timing measurement conditions are illustrated in
2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section
3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times
4. Timing measurement conditions are illustrated in
5. RST# is asserted and de-asserted asynchronously with respect to the CLK signal.
6. All PCI and CardBus interface output drivers are floated when RST# is active.
7. CardBus minimum times are specified with a 0 pF equivalent load. Maximum times are specified with a 30 pF
•
4.2.3.2.
and input setup times than bussed signals. All other signals are bussed.
equivalent load. Actual test loads may vary but must be correlated to these loads.
FLA6:0, FLD7:0, FLCS#, FLOE#, and FLWE# have the same functions for Flash and modem.
t
t
t
t
t
t
t
t
T
T
val
val(ptp)
on
off
su
su(ptp)
h
rst
Symbol
rst-clk
rst-off
provides the timing parameters for the Flash interface signals. The timing parameters are
Figure 26
PCI CLK to Signal Valid Delay
CardBus CLK to Signal Valid Delay
PCI CLK to Signal Valid Delay (point-
to-point)
Float to Active Delay
Active to Float Delay
Input Setup Time to CLK
PCI Input Setup Time to CLK (point-to-
point)
Input Hold Time from CLK
Reset Active Time After Power Stable
PCI Reset Active Time After CLK
Stable
CardBus Reset Active Time After CLK
Stable
Reset Active to Output Float Delay
and
Figure
Parameter
27.
Figure
Figure
24.
25.
Min
100
100
10
2
2
2
2
7
0
1
Networking Silicon — 82551QM
Max
11
18
12
28
40
clocks
clocks
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
PP
Notes
1, 2, 3
1, 2, 3
signal in the Flash
1, 7
3, 4
3, 4
5, 6
1
1
5
5
5
5
97