LU82551QM Intel, LU82551QM Datasheet - Page 59

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

9.1.6
9.1.7
9.1.8
9.1.9
Datasheet
Note: Bit 3 is set to 1b only if the value 00001000b (8h) is written to this register, and bit 4 is set to 1b
PCI Cache Line Size Register
In order for the 82551QM to support the Memory Write and Invalidate (MWI) command, the
82551QM must also support the Cache Line Size (CLS) register in PCI Configuration space. The
register supports only cache line sizes of 8 and 16 Dwords. Any value other than 8 or 16 that is
written to the register is ignored and the 82551QM does not use the MWI command. If a value
other than 8 or 16 is written into the CLS register, the 82551QM returns all zeroes when the CLS
register is read. The figure below illustrates the format of this register.
only if the value of 00010000b (16h) is written to this register. All other bits are read only and will
return a value of 0b on read.
The BIOS is expected to write to this register. Therefore, the 82551QM driver should not write to
it.
PCI Latency Timer
The Latency Timer register is a byte wide register. When the 82551QM is acting as a bus master,
this register defines the amount of time, in PCI clock cycles, that it may own the bus.
PCI Header Type
The Header Type register is a byte read only register. It is equal to 00h for a single function
Ethernet card and 80h for a combination Ethernet and modem card. The value of the header type is
set by the EEPROM
will read the next configuration registers bank at offset 100h.
PCI Base Address Registers
One of the most important functions for enabling superior configurability and ease of use is the
ability to relocate PCI devices in address spaces. The 82551QM contains three types of Base
Address Registers (BARs). Two are used for memory mapped resources, and one is used for I/O
mapping. Each register is 32 bits wide. The least significant bit in the BAR determines whether it
represents a memory or I/O space. The figures below show the layout of a BAR for both memory
and I/O mapping. After determining this information, power-up software can map the memory and
I/O controllers into available locations and proceed with system boot. In order to do this mapping
Figure 18. Cache Line Size Register
7
0
(Section 5.7, “Serial EEPROM
6
0
5
0
RW
4
Interface”). In a dual function card, the OS
RW
3
Networking Silicon — 82551QM
2
0
1
0
0
0
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