LU82551QM Intel, LU82551QM Datasheet - Page 76

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
10.1.11
10.1.12
10.1.13
70
Table 31. General Control Register
Table 32. General Status Register
Note: The PMDR is initialized at ALTRST# reset only.
General Control Register
The General Control register is a byte register and is described below. The General Control register
is used in CardBus mode only.
General Status Register
The General Status register is used in CardBus mode only and is a byte register that indicates the
link status of the 82551QM.
Ethernet Card Status Change Registers
The PME signal used in PCI systems is replaced by the Card Status Change (CSTSCHG) signal in
CardBus systems. The CardBus specification requires the use of control/status registers related to
CSTSCHG. There are four event related registers.
7:2
1
0
7:3
2
1
0
1. Function Event Register: Specifies the event that changed status
2. Function Event Mask Register: Masks CSTSCHG signal assertion for specified events
3. Function Present State Register: Reflects the current state of each condition that may cause a
4. Force Event Register: Simulates status change events for troubleshooting purposes
Bits
Bits
status change or interrupt
000000b
0b
0b
00000b
--
--
0b
Default
Default
Read Only
Read/Write
Read/Write
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Reserved. These bits are reserved and should be set to 000000b.
Deep Power-Down on Link Down Enable. If a 1b is written to this
field, the 82551QM may enter a deep power-down state (sub-3 mA) in
the D2 and D3 power states while the link is down.
In this state, the 82551QM does not keep link integrity. This state is not
supported for point-to-point connection of two end stations.
Clock Run Signal Disable. If this bit is set to 1b, then the 82551QM
always requests the PCI clock signal. This mode can be used to
overcome potential receive overruns caused by Clock Run signal
latencies over 5 µs.
Reserved. These bits are reserved and should be set to 00000b.
Duplex Mode. This bit indicates the wire duplex mode: full duplex (1b)
or half duplex (0b).
Speed. This bit indicates the wire speed: 100 Mbps (1b) or 10 Mbps
(0b).
Link Status Indication. This bit indicates the status of the link: valid
(1b) or invalid (0b).
Description
Description
Datasheet