LU82551QM Intel, LU82551QM Datasheet - Page 33

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

5.3.1.2
5.3.1.3
5.3.1.4
Datasheet
1. For a topology of two 82551QM devices connected by a crossed twisted-pair Ethernet cable, the deep power-down mode should be
disabled. If it is enabled, the two devices may not detect each other if the operating system places them into a low power state before both
nodes become active.
D1 Power State
For a device to meet the D1 power state requirements, as specified in the Advanced Configuration
and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus transmission or
interrupts; however, bus reception is allowed. Therefore, device context may be lost and the
82551QM does not initiate any PCI activity. In this state, the 82551QM responds only to PCI
accesses to its configuration space and system wake-up events.
The 82551QM retains link integrity and monitors the link for any wake-up events such as wake-up
packets or link status change. Following a wake-up event, the 82551QM asserts the PME# signal to
alert the PCI system or the CSTSCHG signal for a CardBus system.
D2 Power State
The ACPI D2 power state is similar in functionality to the D1 power state. If the bus is in the B2
bus power state, the 82551QM will consume less current than it does in the D1 state. In addition to
D1 functionality, the 82551QM can provide a lower power mode with wake-on-link status change
capability. The 82551QM may enter this mode if the link is down while the 82551QM is in the D2
state. In this state, the 82551QM monitors the link for a transition from an invalid link to a valid
link. The 82551QM will not attempt to keep the link alive by transmitting idle symbols or link
integrity pulses.
configuration bit in the Power Management Driver Register (PMDR).
D3 Power State
In the D3 power state, the 82551QM has the same capabilities and consumes the same amount of
power as it does in the D2 state. However, it enables the PCI system to be in the Bus Power 3 (B3)
state. If the PCI system is in the B3 state (in other words, no PCI power is present), the 82551QM
provides wake-up capabilities if it is connected to an auxiliary power source in the system. If PME
is disabled, the 82551QM does not provide wake-up capability or maintain link integrity. In this
mode, the 82551QM consumes minimal power.
The 82551QM enables a system to be in a sub-5 watt state (low power state) and still be virtually
connected. More specifically, the 82551QM supports full wake-up capabilities while it is in the D3
cold state. The 82551QM can be connected to an auxiliary power source (V
to provide wake-up functionality while the PCI power is off. The typical current consumption of
the 82551QM is 125 mA at 3.3 V and a dual power plane is not required. If connected to an
auxiliary power source, the 82551QM receives all of its power from the auxiliary source in all
power states. When connected to an auxiliary power supply, the 82551QM must have a status
indicator of whether the power supply is valid (in other words, auxiliary power is stable). The
indication is received at the AUXPWR pin, as described next.
1
The sub-10 mA state due to an invalid link can be enabled or disabled by a
Networking Silicon — 82551QM
AUX
), which enables it
27