LU82551QM Intel, LU82551QM Datasheet - Page 75

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

10.1.10
Datasheet
Table 30. Power Management Driver Register
Power Management Driver Register
The 82551QM provides an indication in memory and I/O space that a wake-up event has occurred.
It is located in the Power Management Driver (PMDR). The PMDR is used for CardBus mode
only.
31
30
29
28
27
26
25
24
Bits
0b
0b
0b
0b
0b
0b
0b
0b
Default
Read/Clear
Read/Clear
Read/Clear
Read Only
Read Only
Read/Clear
Read/Clear
Read/Clear
Read/Write
Link Status Change Indication. The link status change bit is set
following a change in link status and is cleared by writing a 1b to it.
Magic Packet*. This bit is set when a Magic Packet is received
regardless of the Magic Packet wake-up disable bit in the configuration
command and the PME Enable bit in the Power Management Control/
Status Register. This bit is cleared by writing 1b to it.
Interesting Packet. This bit is set when an “interesting” packet is
received. Interesting packets are defined by the 82551QM packet
filters. This bit is cleared by writing 1b to it.
Reserved. This bit is reserved and should be set to 0b.
GCL Enable. This bit is set to 1b when the 82551QM is in GCL mode
(in other words, the 82551QM handles management packets). If the
GCL Enable bit is set to 0b, the 82551QM does not handle
management packets. In this mode, management packets are handled
by an external TCO controller.
Force TCO Indication. This bit is reserved for testing.
TCO Request. This bit is set to 1b when the 82551QM is busy with
TCO activity.
PME Status. This bit is a reflection of the PME Status bit in the Power
Management Control/Status Register (PMCSR). It is set upon a wake-
up event and is independent of the PME Enable bit.
This bit is cleared by writing 1b to it. This also clears the PME Status
bit in the PMCSR and de-asserts the PME signal. In a CardBus
system, if 1b is written to this field, the General Wake-up (GWAKE) bit
in the Function Event register is cleared.
Description
Networking Silicon — 82551QM
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