LU82551QM Intel, LU82551QM Datasheet - Page 36

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
5.3.2
5.3.2.1
30
Note: The wake-up event is supported only if the PME Enable bit in the Power Management Control/
The following tables list the functionality at the different power states for the 82551QM.
Wake-up Events
There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two
events are detailed below.
Status (PMCSR) register is set. The PMCSR is described in
Control/Status Register
“Interesting” Packet Event
In the power-down state, the 82551QM is capable of recognizing “interesting” packets. The
82551QM supports pre-defined and programmable packets that can be defined as any of the
following:
•
•
•
•
•
•
•
Table 13. Functionality at the Different Power States
Address Resolution Protocol (ARP) Packets (with Multiple IP addresses)
Direct Packets (with or without type qualification)
Magic Packet*
Neighbor Discovery Multicast Address Packet (“ARP” in IPv6 environment)
NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)
Internetwork Package Exchange* (IPX*) Diagnostic Packet
TCO Packet
D0u
D0a
D1
D2
D3 (with power)
Dx (x>0 without
PME#)
Power State
(PMCSR)”.
Don’t care
Valid
Invalid
Valid
Invalid
Valid
Invalid
Valid
Invalid
Don’t care
Link
•
•
Full functionality at full power and wake on an
invalid link
Full functionality at full power and wake on a valid
link
•
•
•
•
Same functionality as D1 (link valid)
Detection for valid link and no link integrity
Same functionality as D1 (link valid)
Detection for valid link and no link integrity
No wake-up functionality
Note: If the TCO bit is set in the EEPROM, the
82551QM will not disable the link function and will
consume power as in the D2 state.
Power-up state
PCI slave access
Wake-up on “interesting” packets and link
invalid
PCI configuration access
Wake on link valid
PCI configuration access
Section 9.1.21, “Power Management
Functionality
Datasheet