LU82551QM Intel, LU82551QM Datasheet - Page 78

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
10.1.13.2
10.1.13.3
72
Table 34. LAN Function Event Mask Register
Table 35. LAN Function Present State Register
LAN Function Event Mask Register
The Function Event Mask register masks CSTSCHG and INTA# assertion.
LAN Function Present State Register
The Function Present State register reflects the current state of the LAN function that may cause a
status change or interrupt.
31:16
15
14
13:7
6:5
4
3
2
1
0
31:16
15
14:5
4
Bits
Bits
Reserved
INTR
WKUP
Reserved
PWM
BAM
GWAKE
Reserved
Reserved
Reserved
Reserved
Reserved
INTR
Reserved
GWAKE
Function
Function
0
0b
0b
0
0
0b
0b
0b
0b
0b
0
0
0
0
Default
Default
Bits [31:16] are reserved in the CardBus Specification.
This bit is the interrupt mask. When this bit equals 0b, it masks the
Ethernet function INTA# line but has no effect on the LAN Function
Event register. The Ethernet function can assert the INTA# signal only
when both fields are enabled: the interrupt bit and the “M” bit in the
System Control Block (SCB) register within the CSR space. The
interrupt mask bit affects the INTA# masking.
This bit is the wake-up mask. When this bit equals 0b, it masks the
Ethernet function CSTSCHG signal but has no effect on the LAN
Function Event register. This bit is dependent on bit 4 of this register.
Bits [13:7] are reserved in the CardBus Specification.
These bits are used for Pulse Width Modulation Binary Audio Enable
(PWM BAM). Note that the PWM BAM bits are not applicable for LAN.
This bit is the general wake-up mask. When this bit equals 0b, it masks
the Ethernet function wake-up events towards the CSTSCHG signal. It
has no effect on the LAN Function Event register. The 82551QM can
assert the CSTSCHG signal in the following configuration of masked
bits: wake-up bit AND general wake-up bit, or PME Enable bit in the
PMCSR register only.
Bit 3 is reserved in the CardBus Specification.
Reserved.
Reserved.
Bit 0 is reserved in the CardBus Specification.
Bits [31:16] are reserved in the CardBus Specification.
This bit is used for interrupts. It reflects the current state of the Ethernet
source of the interrupt regardless of the mask value. It is set when the
Ethernet function has a pending interrupt and cleared when the
software driver acknowledges all active interrupts through the SCB
Command Word.
Bits [14:5] are reserved in the CardBus Specification.
This bit is used for general wake-up. It reflects the current state of the
Ethernet source of CSTSCHG. It is a logical OR result of the gated
three most significant bits in the PMDR: Link Status Change, Magic
Packet, and Interesting Packet. The Link Status change bit is gated by
the Link Status Change Wake Enable bit in the Configuration
command. The Magic Packet bit is gated by the Magic Packet Wake-
up disable bit in the Configuration command. The Interesting Packet bit
is gated by the programmable filter command.
Description
Description
Datasheet