LU82551QM Intel, LU82551QM Datasheet - Page 22

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
5.1.2
5.2
5.2.1
16
Table 11. Initialization Effects
Table 12. Initialization Effects on TCO
Initialization Effects on TCO Functionality
The 82551QM has the ability to be controlled by two masters, the host CPU on the PCI bus and the
TCO controller on the SMB. The 82551QM may be initialized by the PCI bus during SMB
operation. The table below lists the effect of those sources:
a. ISOLATE# acts as reset on its trailing edge. While the 82551QM is in the D3 power state, the RST# initializes the
b. SMB commands in process will be terminated immediately.
PCI and CardBus Interface
Bus Operations
After configuration, the 82551QM is ready for its normal operation. As a Fast Ethernet Controller,
the role of the 82551QM is to access transmitted data or deposit received data. In both cases the
82551QM, as a bus master device, will initiate memory cycles by way of the PCI bus.
Power
management
event reset
Statistic
counters reset
Sampling of
configuration
input pins
ALTRST#, RST#, or
ISOLATE#
D3 to D0 transition
Software Reset,
Selective Reset, or D3 to
D0 transition
Initialization Source
82551QM on the trailing edge.
a
Internal
POR
?
?
?
The SMB is terminated instantaneously.
The SMB cycle is aborted. During SMB read
commands, the 82551QM transfers zeros until the
end of the cycle. An SMB write cycle has no effect on
the 82551QM. The 82551QM asserts the
SMB_ALERT# after a D3 to D0 transition. The
82551QM indicates its initialization status to the TCO
controller via an active initialization bit in the Status
Word.
The SMB cycle is aborted. During SMB read
commands, the 82551QM transfers zeros until the
end of the cycle. An SMB write cycle has no effect on
the 82551QM. After a software reset, the 82551QM
reports its initialization in the same manner as in a D3
to D0 transition.
ALTRST#
?
?
?
Clear only
auxiliary
SMB Behavior
present
power
RST#
if no
?
?
ISOLATE#
Clear only
auxiliary
present
power
if no
--
?
b
Transition
D3 to D0
--
--
?
Initialized to inactive
Initialized to inactive
Unaffected
Status and Receive
Software
Reset
--
--
?
Enable
Datasheet
Selective
Reset
--
--
--