LU82551QM Intel, LU82551QM Datasheet - Page 77

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

10.1.13.1
Datasheet
1. For a combination LAN/modem card, the 82551QM implements two independent sets of card status change registers. Each set controls its
Table 33. LAN Function Event Register
function separately.
Note: Access to the CSTSCHG registers in PCI mode is not allowed.
These CardBus registers are used by software to determine which event has occurred, to manage
the event, and to control the CSTSCHG signal.
The 82551QM supports only the interrupt and general wake-up event bits in the card status change
registers
compliant OS. They are initialized by a power-up reset on the ALTRST# pin.
The location of these registers should be specified within the configuration space pointing to offset
address 30h of the CSR.
LAN Function Event Register
The Function Event register specified the event that changed the status.
31:16
15
14:5
4
3
2
1
0
Bits
1
. These registers complement the PCI Power Management registers in a non-ACPI
Reserved
INTR
Reserved
GWAKE
Reserved
Reserved
Reserved
Reserved
Function
0
0b
0
0b
0b
0b
0b
0b
Default
Bits [31:16] are reserved in the CardBus Specification.
This bit is used for as the interrupt bit. It is set when the Ethernet
interrupt source is set, regardless of the mask value. It is cleared when
the OS writes 1b to this field and the interrupt source has been
serviced. Writing 0b to this field has no effect.
Bits [14:5] are reserved in the CardBus Specification.
This bit is used for general wake-up. It is set when the Ethernet wake-
up source is set, regardless of the mask value. Writing 1b to this field
clears this bit and the PME Status bit in the PMCSR. Writing 0b to this
field has no effect. Note that writing 1b to the PME Status bit in the
PMCSR has the same effect.
Bit 3 is reserved in the CardBus Specification.
Reserved.
Reserved.
Bit 0 is reserved in the CardBus Specification.
Description
Networking Silicon — 82551QM
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