LU82551QM Intel, LU82551QM Datasheet - Page 64

• Manufacturer Part Number: LU82551QM
• Manufacturer: Intel

Specifications of LU82551QM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551QM — Networking Silicon
9.1.16
9.1.17
9.1.18
9.1.19
9.1.20
58
Table 20. Power Management Capability Register
Minimum Grant Register
The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not
applicable to non-master devices. It defines the amount of time the bus master wants to retain PCI
bus ownership when it initiates a transaction. The default value of this register for the 82551QM is
08h.
Maximum Latency Register
The Maximum Latency (Max_Lat) register is an optional read only register for bus masters and is
not applicable to non-master devices. This register defines how often a device needs to access the
PCI bus. The default value of this register for the 82551QM is 18h.
Capability ID Register
The Capability ID is a byte register. It signifies whether the current item in the linked list is the
register defined for PCI Power Management. PCI Power Management has been assigned the value
of 01h. The 82551QM is fully compliant with the PCI Power Management Specification, Revision
2.2.
Next Item Pointer
The Next Item Pointer is a byte register. It describes the location of the next item in the 82551QM’s
capability list. Since power management is the last item in the list, this register is set to 0b.
Power Management Capabilities Register
The Power Management Capabilities register is a word read only register. It provides information
on the capabilities of the 82551QM related to power management. The 82551QM reports a value
of FE21h if it is connected to an auxiliary power source and 7E21h otherwise. It indicates that the
82551QM supports wake-up in the D3 state if power is supplied, either V
31:27
26
25
24:22
21
Bits
00011b
(no V
11111b
(V
1b
1b
000b
1b
Default
AUX
AUX
)
)
Read Only
Read Only
Read Only
Read Only
Read Only
Read/Write
PME Support. This five-bit field indicates the power states in which
the 82551QM may assert PME#. The 82551QM supports wake-up in
all power states if it is fed by an auxiliary power supply (V
D0, D1, D2, and D3
D2 Support. If this bit is set, the 82551QM supports the D2 power
state.
D1 Support. If this bit is set, the 82551QM supports the D1 power
state.
Auxiliary Current. This field reports whether the 82551QM
implements the Data registers. The auxiliary power consumption is
the same as the current consumption reported in the D3 state in the
Data register.
Device Specific Initialization (DSI). The DSI bit indicates whether
special initialization of this function is required (beyond the standard
PCI configuration header) before the generic class device driver is
able to use it. DSI is required for the 82551QM after D3-to-D0 reset.
hot
if it is fed by PCI power.
Description
cc
or V
AUX
.
AUX
Datasheet
) and