PIC18F45K22-I/P

Manufacturer Part NumberPIC18F45K22-I/P
Description40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
ManufacturerMicrochip Technology Inc.
PIC18F45K22-I/P datasheet
 

Specifications of PIC18F45K22-I/P

A/d Inputs28-Channel, 10-BitComparators2
Cpu Speed16 MIPSEeprom Memory256 Bytes
Input Output35InterfaceI2C/SPI/UART/USART
Memory TypeFlashNumber Of Bits8
Package Type40-pin PDIPProgrammable Memory32K Bytes
Ram Size1.5K BytesSpeed64 MHz
Temperature Range–40 to 125 °CTimers3-8-bit, 4-16-bit
Voltage, Range1.8-5.5 VLead Free Status / Rohs StatusRoHS Compliant part Electrostatic Device
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PIC18(L)F2X/4XK22
Data Sheet
28/40/44-Pin, Low-Power,
High-Performance Microcontrollers
with nanoWatt XLP Technology
Preliminary
 2010 Microchip Technology Inc.
DS41412D

PIC18F45K22-I/P Summary of contents

  • Page 1

    ... High-Performance Microcontrollers  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 28/40/44-Pin, Low-Power, with nanoWatt XLP Technology Preliminary Data Sheet DS41412D ...

  • Page 2

    ... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary logo, MPLAB, PIC, PICmicro, PICSTART, ® DSCs ® code hopping EE OQ  2010 Microchip Technology Inc. ...

  • Page 3

    ... DAC with positive and negative reference selection • Charge Time Measurement Unit (CTMU) module: - Supports capacitive touch sensing for touch screens and capacitive switches  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Extreme Low-Power Management with nanoWatt XLP: • Sleep mode: 20 nA, typical • ...

  • Page 4

    ... PIC18(L)F44K22 16K 8192 768 PIC18(L)F45K22 32K 16384 1536 PIC18(L)F46K22 64k 32768 3896 Note 1: One pin is input only. 2: Channel count includes internal FVR and DAC channels. DS41412D-page 4 MSSP 256 256 256 1024 256 256 256 1024 Preliminary  2010 Microchip Technology Inc. ...

  • Page 5

    ... Pin Diagrams 28-pin PDIP, SOIC, SSOP MCLR/V PP (1) 28-pin QFN, UQFN RA2 RA3 RA4 RA5/ V RA7 RA6 Note 1: The 28-pin UQFN package is available only for PIC18(L)F23K22 and PIC18(L)F24K22.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 28 1 /RE3 27 2 RA0 26 3 RA1 4 25 RA2 5 ...

  • Page 6

    ... RD1 20 21 RC0 30 1 RA6 29 2 RA7 PIC18(L)F4XK22 RE2 25 6 RE1 7 24 RE0 RA5 9 21 RA4 10 Preliminary RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2  2010 Microchip Technology Inc. ...

  • Page 7

    ... Pin Diagrams (Cont.’d) 44-pin TQFP RC7 RD4 RD5 RD6 RD7 RB0 RB1 RB2 RB3 44-pin QFN RC7 RD4 RD5 RD6 RD7 RB0 RB1 RB2  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 RC0 2 32 RA6 RA7 PIC18(L)F4XK22 RE2 7 RE1 8 26 RE0 9 25 ...

  • Page 8

    ... SCL1 SDI1/ SDA1 SDO1 CCP3/ TX1/CK1 (4) P3A P3B RX1/DT1 Preliminary T0CKI OSC2/ CLKO OSC1/ CLKI INT0 Y INT1 Y INT2 Y Y T5G IOC Y T1G IOC Y (2) T3CKI IOC Y PGC IOC Y PGD SOSCO/ T1CKI (2) T3CKI T3G SOSCI T5CKI MCLR  2010 Microchip Technology Inc. ...

  • Page 9

    ... RD6 AN26 RD7 AN27 RE0 AN5 Note 1: CCP2 multiplexed in fuses. 2: T3CKI multiplexed in fuses. 3: CCP3/P3A multiplexed in fuses. 4: P2B multiplexed in fuses.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 C12IN0- C12IN1- C2IN REF DACOUT C1IN REF C1OUT SRQ C2OUT SRNQ HLVDIN SRI FLT0 C12IN3- CTED1 ...

  • Page 10

    ... PIC18(L)F2X/4XK22 TABLE 2: PIC18(L)F4XK22 PIN SUMMARY (CONTINUED RE1 AN6 RE2 AN7 RE3 7 28 30, 31 — — 12 33, 34 Note 1: CCP2 multiplexed in fuses. 2: T3CKI multiplexed in fuses. 3: CCP3/P3A multiplexed in fuses. 4: P2B multiplexed in fuses. DS41412D-page 10 P3B CCP5 Preliminary  2010 Microchip Technology Inc. Y MCLR ...

  • Page 11

    ... Packaging Information............................................................................................................................................................. 463 Appendix A: Revision History............................................................................................................................................................ 481 Appendix B: Device Differences........................................................................................................................................................ 482 Index ................................................................................................................................................................................................. 483 The Microchip Web Site .................................................................................................................................................................... 493 Customer Change Notification Service ............................................................................................................................................. 493 Customer Support ............................................................................................................................................................................. 493 Reader Response ............................................................................................................................................................................. 494 Product Identification System ........................................................................................................................................................... 495  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Preliminary DS41412D-page 11 ...

  • Page 12

    ... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS41412D-page 12 to receive the most current information on all of our products. Preliminary  2010 Microchip Technology Inc. ...

  • Page 13

    ... PIC18LF24K22 • PIC18F25K22 • PIC18LF25K22 • PIC18F26K22 • PIC18LF26K22 • PIC18F43K22 • PIC18LF43K22 • PIC18F44K22 • PIC18LF44K22 • PIC18F45K22 • PIC18LF45K22 • PIC18F46K22 • PIC18LF46K22 This family offers the advantages of all PIC18 microcontrollers – namely, high performance at an economical price – with the addition of high-endurance, Flash program memory ...

  • Page 14

    ... All other features for devices in this family are identical. These are summarized in The pinouts for all devices are listed in the pin summary tables: Table 1 and Table Table 1-2 and Table 1-3. Preliminary  2010 Microchip Technology Inc. Figure 1-1. Table 1-1. 2, and I/O description tables: ...

  • Page 15

    ... TABLE 1-1: DEVICE FEATURES  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Preliminary DS41412D-page 15 ...

  • Page 16

    ... Reset Timer Precision FVR Band Gap Reset Reference Timer1 Timer2 Timer3 Timer4 CTMU Timer5 Timer6 MSSP1 EUSART1 SR Latch EUSART2 MSSP2 Preliminary PORTA RA0:RA7 PORTB RB0:RB7 PORTC RC0:RC7 PORTD RD0:RD7 PORTE RE0:RE2 (1) RE3 DAC ADC FVR 10-bit  2010 Microchip Technology Inc. ...

  • Page 17

    ... Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Pin Buffer Type ...

  • Page 18

    ... Analog Analog input 8. I/O TTL Digital I/ CTMU Edge 2 input. O CMOS Enhanced CCP2 PWM output. I/O ST Capture 2 input/Compare 2 output/PWM 2 output. O — SPI data out (MSSP2). I Analog Comparators C1 and C2 inverting input. I Analog Analog input 9. Preliminary  2010 Microchip Technology Inc. 2 C™ mode ...

  • Page 19

    ... Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Pin Buffer Description ...

  • Page 20

    ... TTL Digital I/O. O CMOS Enhanced CCP3 PWM output EUSART 1 asynchronous receive. I/O ST EUSART 1 synchronous data (see related TXx/CKx). I Analog Analog input 19 Digital input. P Programming voltage input Active-Low Master Clear (device Reset) input. Preliminary  2010 Microchip Technology Inc. 2 C™ mode ...

  • Page 21

    ... Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Pin Buffer ...

  • Page 22

    ... Analog Analog input 8. RB3 I/O TTL Digital I/O. CTED2 I ST CTMU Edge 2 input. (2) P2A O CMOS Enhanced CCP2 PWM output. (2) CCP2 I/O ST Capture 2 input/Compare 2 output/PWM 2 output. C12IN2- I Analog Comparators C1 and C2 inverting input. AN9 I Analog Analog input 9. Preliminary Description  2010 Microchip Technology Inc. ...

  • Page 23

    ... Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Pin Buffer ...

  • Page 24

    ... AN20 I Analog Analog input 20. RD1 I/O TTL Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output. SDI2 I ST SPI data in (MSSP2). 2 SDA2 I C™ data I/O (MSSP2). AN21 I Analog Analog input 21. Preliminary Description 2 C™ 2 C™  2010 Microchip Technology Inc. ...

  • Page 25

    ... Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Pin Buffer ...

  • Page 26

    ... Analog Analog input 7. /MCLR RE3 I ST Digital input Programming voltage input. PP MCLR I ST Active-low Master Clear (device Reset) input — Positive supply for logic and I/O pins — Ground reference for logic and I/O pins Preliminary Description  2010 Microchip Technology Inc. ...

  • Page 27

    ... PLLEN (OSCTUNE<6>) 5. HFOFST (CONFIG3H<3>) 6. IRCF<2:0> (OSCCON<6:4>) 7. MFIOSEL (OSCCON2<4>) 8. INTSRC (OSCTUNE<7>)  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 The HFINTOSC, MFINTOSC and LFINTOSC are factory calibrated high, medium and low-frequency oscillators, respectively, which are used as the internal clock sources. Figure 2-1 /4) for OSC ...

  • Page 28

    ... PLL Select (5) FOSC<3:0> Primary Oscillator 0 4xPLL INTOSC 1 INTSRC 3 3 HF HF-500 kH Z HF-250 kH Z INTOSC HF-31. MF-500 kH Z MF-250 kH Z MF-31. LF-31.25 kHz Preliminary Low-Power Mode Event Switch (SCS<1:0>) 2 Secondary Oscillator 01 (3) (4) Primary 0 Clock 00 1 INTOSC 1x  2010 Microchip Technology Inc. ...

  • Page 29

    ... On device Resets, the output frequency of the internal oscillator is set to the default frequency of 1 MHz.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 2.2.3 LOW FREQUENCY SELECTION When a nominal output frequency of 31.25 kHz is selected (IRCF< ...

  • Page 30

    ... FOSC (any source) OSC1/OSC2 (external source) INTOSC (internal source) INTOSC (internal source) DS41412D-page 30 FIGURE 2-3: FOSC<3:0> = 100x PLLCFG 3 PLLEN INTOSC FOSC<3:0> PLLCFG 0000-1111 0 0000-0111 1 1010-1111 0 1000-1001 x x Preliminary PLL SELECT BLOCK DIAGRAM PLL Select PLLEN PLL Select  2010 Microchip Technology Inc. ...

  • Page 31

    ... SECONDARY OSCILLATOR AND EXTERNAL CLOCK INPUTS SOSCEN EN SOSCI Secondary Oscillator SOSCO T1CKI T3G SOSCEN T3CKI SOSCEN SOSCEN T3CKI T1G T5CKI T5G  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 SOSCGO T1SOSCEN T3SOSCEN T5SOSCEN SOSCOUT T3G 0 1 T3CMX T1G T5G Preliminary To Clock Switch Module 1 T1CLK_EXT_SRC ...

  • Page 32

    ... INTOSC source may be determined by the INTSRC bit in OSCTUNE and the MFIOSEL bit in OSCCON2. 3: Default output frequency of HFINTOSC on Reset. DS41412D-page 32 R/W-1 R-q R-0 (1) OSTS HFIOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (3) Preliminary R/W-0 R/W-0 SCS<1:0> bit depends on condition x = Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 33

    ... MFIOFS: MFINTOSC Frequency Stable bit 1 = MFINTOSC is stable 0 = MFINTOSC is not stable bit 0 LFIOFS: LFINTOSC Frequency Stable bit 1 = LFINTOSC is stable 0 = LFINTOSC is not stable Note 1: The SOSCGO bit is only reset on a POR Reset.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-0/0 R/W-0/u R/W-1/1 (1) MFIOSEL SOSCGO PRISD U = Unimplemented bit, read as ‘ ...

  • Page 34

    ... Section 2.10 Mode”). Oscillator Delay Oscillator Warm-Up Delay (T ) WARM 2 instruction cycles 1 cycle of each 1024 Clock Cycles (OST) 1024 Clock Cycles (OST s (approx.) EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN ® PIC MCU (1) I/O OSC2/CLKOUT Overview”.  2010 Microchip Technology Inc. ...

  • Page 35

    ... The value of R varies with the Oscillator mode F selected (typically between 2 M M.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Note 1: Quartz according manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application ...

  • Page 36

    ... The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. ) values EXT Preliminary (High-Frequency Internal via software using the (Register 2-3). (Register 2-3). (Low-Frequency Internal for more information. /4 (CLKOUT). In both OSC Section 24.0 “Special Features of  2010 Microchip Technology Inc. ...

  • Page 37

    ... The PLLEN bit is active only when the HFINTOSC is the primary clock source (FOSC<2:0> = 100X) and the selected frequency is 8 MHz or 16 MHz (IRCF<2:0> = 11x). Otherwise, the PLLEN bit is unavailable and always reads ‘0’.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 as the Power-up Timer (PWRT), Watchdog Timer ...

  • Page 38

    ... If the measured time is much less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register. Preliminary Compensating with the EUSART Compensating with the Timers Compensating with the CCP Module in Capture Mode  2010 Microchip Technology Inc. ...

  • Page 39

    ... MHz MHz. The PLL then multiplies the oscillator output frequency produce an internal clock frequency MHz. Oscillator frequencies below 4 MHz should not be used with the PLL.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 2.6.2 PLL IN HFINTOSC MODES The 4x frequency multiplier can be used with the ...

  • Page 40

    ... HFINTOSC is stable. When the HFOFST bit is set, the main system clock starts immediately. In either case, the HFIOFS bit of the OSCCON register can be read to determine whether the HFINTOSC is operating and stable. Preliminary , following POR, while CSD  2010 Microchip Technology Inc. ...

  • Page 41

    ... IRCF<2:0> bits of the OSCCON register. • When SCS<1:0> = 01, the system clock source is the 32.768 kHz secondary oscillator shared with Timer1, Timer3 and Timer5.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 OSC1 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 ...

  • Page 42

    ... SCS<1:0> (of the OSCCON register) = 00. • FOSC<2:0> bits of the CONFIG1H Configuration register are configured for LP mode. Two-Speed Start-up mode becomes active after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. Preliminary  2010 Microchip Technology Inc. ...

  • Page 43

    ... New Clock New Clk Ready IRCF <2:0> Select Old System Clock Note 1: Start-up time includes T OST  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 2.10.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC< ...

  • Page 44

    ... Safe clock monitoring in either HS, XT oscillator modes then the IESO config- uration bit should also be set so that the clock will automatically switch from the internal clock to the external oscillator when the OST times out. Preliminary switchover has successfully  2010 Microchip Technology Inc. ...

  • Page 45

    ... CONFIG1H IESO FCMEN PRICLKEN PLLCFG CONFIG2L — — CONFIG3H MCLRE — Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Clock Sources.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Oscillator Failure Test Test Bit 5 Bit 4 Bit 3 TMR0IE INT0IE ...

  • Page 46

    ... PIC18(L)F2X/4XK22 NOTES: DS41412D-page 46 Preliminary  2010 Microchip Technology Inc. ...

  • Page 47

    ... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 3.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • ...

  • Page 48

    ... T If the IRCF bits were previously at a non-zero value INTSRC was set before setting SCS1 and the INTOSC source was already stable, then the HFIOFS or MFIOFS bit will remain set. Preliminary  2010 Microchip Technology Inc. INTOSC (MFINTOSC or Figure 3-1), ...

  • Page 49

    ... These intervals are not shown to scale. OST OSC PLL 2: Clock transition typically occurs within 2-4 T TABLE 3-2: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS IRCF<2:0> INTSRC 000 0 000 1 000 1 010 or 001 x 010 or 001 x  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 n-1 n (1) Clock Transition OSC (1) (1) OST ...

  • Page 50

    ... Peripheral Clock Program Counter SCS<1:0> bits Changed Note1 1024 (approx). These intervals are not shown to scale. OST OSC PLL 2: Clock transition typically occurs within 2-4 T DS41412D-page (1) PLL (1) OST n-1 n Clock (2) Transition PC OSTS bit Set . OSC Preliminary  2010 Microchip Technology Inc. ...

  • Page 51

    ... Clock Peripheral Clock Sleep Program PC Counter  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. ...

  • Page 52

    ... T3SOSCEN or T5SOSCEN) must be set when the SLEEP instruction is executed. 3-7). Otherwise, the main system clock will con- tinue to operate in the previously selected mode and the corresponding IDLE mode will be entered (i.e., PRI_IDLE or RC_IDLE Preliminary Figure 3-7).  2010 Microchip Technology Inc. ...

  • Page 53

    ... Either the HFIOFS or the MFIOFS bits become set, after the HFINTOSC output stabilizes after an interval For information on the IOBST HFIOFS and MFIOFS bits, see Table 3-2.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 T CSD PC Clocks to the HFINTOSC source stabilizes. The HFIOFS and ...

  • Page 54

    ... Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. Preliminary mode (see Section 3.2 “Run Mode”). If the device Section 24.2 “Watchdog Table 3-3.  2010 Microchip Technology Inc. ...

  • Page 55

    ... Section 3.4 “Idle 2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies the Oscillator Start-up Timer. t OST 4: Execution continues during the HFINTOSC stabilization period, T  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Clock Source Exit Delay after Wake-up LP, XT, HS HSPLL T CSD EC, RC ...

  • Page 56

    ... R/W-0 R/W-0 R/W-0 TMR5MD TMR4MD TMR3MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary reducing its power R/W-0 R/W-0 TMR2MD TMR1MD bit Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 57

    ... Module is enabled, Clock Source is connected, module draws digital power bit 0 CCP1MD: CCP1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-0 R/W-0 R/W-0 ...

  • Page 58

    ... Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power DS41412D-page 58 U-0 R/W-0 R/W-0 CTMUMD CMP2MD — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2010 Microchip Technology Inc. R/W-0 R/W-0 CMP1MD ADCMD bit Bit is unknown ...

  • Page 59

    ... PWRT LFINTOSC 11-bit Ripple Counter Note 1: See Table 4-2 for time-out situations. 2: PWRT and OST counters are reset by POR and BOR. See Sections  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. 4.1 RCON Register ...

  • Page 60

    ... It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. DS41412D-page 60 R/W-1/q R-1/q R-1 Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = depends on condition (1) (2) (3) for additional information. Preliminary R/W-q/u R/W-0/q (2) POR BOR bit 0  2010 Microchip Technology Inc. ...

  • Page 61

    ... POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user must manually set the bit to ‘1’ by software following any POR.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 4-2: V ...

  • Page 62

    ... Sleep. If the BOR is disabled, in software or by reentering Sleep before the FVR stabilizes, the BOR circuit will not sense a BOR condition. The FVRST bit of the VREFCON0 register can be used to determine FVR stability. Preliminary and operates as previously  2010 Microchip Technology Inc. ...

  • Page 63

    ... The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset exit from all power-managed modes that stop the external oscillator.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 BOR Operation 4.5.3 PLL LOCK TIME-OUT ...

  • Page 64

    ... DS41412D-page 64 (2) Power-up and Brown-out PWRTEN = 1024 OSC OSC ( 1024 T 1024 T OSC OSC (1) — (1) — (1) — T PWRT T OST T PWRT Preliminary Exit from Power-Managed Mode (2) (2) 1024 OSC 1024 T OSC — — — RISE < PWRT ): CASE OST  2010 Microchip Technology Inc. ...

  • Page 65

    ... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 T PWRT RISE > PWRT T OST Preliminary ): CASE 2 ...

  • Page 66

    ... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST  max. First three stages of the PWRT timer. T PLL DS41412D-page 66 T PWRT T OST T PLL Preliminary  2010 Microchip Technology Inc ...

  • Page 67

    ... SBOREN STKPTR STKFUL STKUNF Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Table 5-2 describes the Reset states for all of the Special Function Registers. The table identifies differences between Power-On Reset (POR)/Brown- Out Reset (BOR) and all other Resets, (i ...

  • Page 68

    ... Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets. DS41412D-page 68 Bit 5 Bit 4 Bit 3 Bit 2 — BORV<1:0> BOREN<1:0> WDPS<3:0> P2BMX T3CMX HFOFST CCP3MX — — — LVP Preliminary Register Bit 1 Bit 0 on Page PWRTEN 352 WDTEN<1:0> 353 PBADEN CCP2MX 354 — STRVEN 355  2010 Microchip Technology Inc. ...

  • Page 69

    ... Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. Data EEPROM is discussed separately in Section 7.0 “Data EEPROM Memory”.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space ...

  • Page 70

    ... Top-of- Stack (TOS) Special File Registers. Data can also be pushed to, or popped from the stack, using these registers. Preliminary 0000h 0008h 0018h FFFFh 10000h 1FFFFFh 200000h  2010 Microchip Technology Inc. ...

  • Page 71

    ... STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 5.1.2.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable ...

  • Page 72

    ... Example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. Preliminary R/W-0 R/W-0 bit Clearable only bit x = Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 73

    ... RETLW nnh RETLW nnh . . .  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 5.1.4.2 Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The ...

  • Page 74

    ... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Fetch INST ( Execute INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Preliminary (Example 5-3 Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1  2010 Microchip Technology Inc. ...

  • Page 75

    ... TSTFSZ 1100 0001 0010 0011 MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 The CALL and GOTO instructions have the absolute program memory instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...

  • Page 76

    ... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Preliminary through 5-7. 5-7 indicate which banks are  2010 Microchip Technology Inc. ...

  • Page 77

    ... FFh = 1100 00h Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h 2FFh 300h 3FFh 400h ...

  • Page 78

    ... Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh also used by SFRs, but are not part of the Access RAM. Users must always use the complete address or load the proper BSR value to access these registers.  2010 Microchip Technology Inc. ...

  • Page 79

    ... FFh = 1100 00h Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...

  • Page 80

    ... Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh also used by SFRs, but are not part of the Access RAM. Users must always use the complete address or load the proper BSR value to access these registers.  2010 Microchip Technology Inc. ...

  • Page 81

    ... Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Data Memory 000h 7 00h ...

  • Page 82

    ... The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. Preliminary Table 5-1 and Table 5-2.  2010 Microchip Technology Inc. ...

  • Page 83

    ... T3CON FD8h STATUS FB0h SPBRGH1 Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: PIC18(L)F4XK22 devices only. 4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Address Name Address FAFh SPBRG1 F87h FAEh RCREG1 F86h FADh TXREG1 ...

  • Page 84

    ... ---x xxxx 0000 0000 xxxx xxxx T0PS<2:0> 1111 1111 SCS<1:0> 0011 q000 MFIOFS LFIOFS 00-0 01x0  2010 Microchip Technology Inc. ...

  • Page 85

    ... SSP2IE BCL2IE Legend unknown unchanged, — = unimplemented value depends on condition Note 1: PIC18(L)F4XK22 devices only. 2: PIC18(L)F2XK22 devices only. 3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. 4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Bit 5 Bit 4 Bit 3 Bit 2 — — — — ...

  • Page 86

    ... TRMT TX9D 0000 0010 OERR RX9D 0000 000x WUE ABDEN 01x0 0-00 xxxx xxxx 2 C Master Mode 0000 0000 UA BF 0000 0000 0000 0000 RSEN SEN 0000 0000 1111 1111 AHEN DHEN 0000 0000  2010 Microchip Technology Inc. ...

  • Page 87

    ... Note 1: PIC18(L)F4XK22 devices only. 2: PIC18(L)F2XK22 devices only. 3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. 4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Bit 5 Bit 4 Bit 3 Bit 2 Capture/Compare/PWM Register 2, High Byte Capture/Compare/PWM Register 2, Low Byte DC2B<1:0> P2DC<6:0> ...

  • Page 88

    ... PIC18(L)F26K22 and PIC18(L)F46K22 devices only. DS41412D-page 88 Bit 5 Bit 4 Bit 3 Bit 2 ANSC5 ANSC4 ANSC3 ANSC2 ANSB5 ANSB4 ANSB3 ANSB2 ANSA5 — ANSA3 ANSA2 Preliminary Value on Bit 1 Bit 0 POR, BOR — — 1111 11-- ANSB1 ANSB0 --11 1111 ANSA1 ANSA0 --1- 1111  2010 Microchip Technology Inc. ...

  • Page 89

    ... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 It is recommended that only BCF, BSF, SWAPF, MOVFF ...

  • Page 90

    ... HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE Preliminary  2010 Microchip Technology Inc. (BSR)”) are ; Clear INDF ; register then ; inc pointer ; All done with ; Bank1? ; NO, clear next ; YES, continue ...

  • Page 91

    ... In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “ ...

  • Page 92

    ... Figure 5-11. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in “Extended Instruction Syntax”. Preliminary  2010 Microchip Technology Inc. Section 25.2.1 ...

  • Page 93

    ... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 000h 060h Bank 0 100h Bank 1 through ...

  • Page 94

    ... PIC18 instruction set. These instructions are executed as described in Section 25.2 “Extended Instruction Bank 0 Bank 1 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Preliminary Set”. 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank  2010 Microchip Technology Inc. ...

  • Page 95

    ... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...

  • Page 96

    ... Note: The EEIF interrupt flag bit of the PIR2 register is set when the write is complete. The EEIF flag stays set until cleared by firmware. Section 24.0 Preliminary Table Latch (8-bit) TABLAT Memory”.  2010 Microchip Technology Inc. ...

  • Page 97

    ... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-0 R/W-x R/W-0 ...

  • Page 98

    ... TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 (1) TABLE READ – TBLPTR<21:0> Preliminary Table 6-1).The Section 6.5 “Writing to the Table Pointer register TBLPTRL 0 TABLE WRITE (1) TBLPTR<n:0>  2010 Microchip Technology Inc. ...

  • Page 99

    ... WORD_EVEN TBLRD*+ MOVFW TABLAT, W MOVF WORD_ODD  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. shows the interface between the internal program memory and the TABLAT ...

  • Page 100

    ... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable block Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary  2010 Microchip Technology Inc. ...

  • Page 101

    ... Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 The long write is necessary for programming the internal Flash. Instruction execution is halted during a long write cycle ...

  • Page 102

    ... TBLWT holding register. Preliminary  2010 Microchip Technology Inc. ...

  • Page 103

    ... C1IF PIE2 OSCFIE C1IE Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during Flash/EEPROM access.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 ; loop until holding registers are full ; point to Flash program memory ; access Flash program memory ; enable write to memory ...

  • Page 104

    ... PIC18(L)F2X/4XK22 NOTES: DS41412D-page 104 Preliminary  2010 Microchip Technology Inc. ...

  • Page 105

    ... FFh). The EEADRH register expands the range to 1024 bytes by adding an additional two address bits.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 7.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2 ...

  • Page 106

    ... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS41412D-page 106 R/W-0 R/W-x R/W-0 FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/S-0 R/S bit Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 107

    ... BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WREN  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...

  • Page 108

    ... Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts Preliminary Section 27.0 “Electrical for write cycle limits. If this is the case,  2010 Microchip Technology Inc. ...

  • Page 109

    ... C1IP PIR2 OSCFIF C1IF PIE2 OSCFIE C1IE Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during EEPROM access. Note 1: PIC18(L)F26K22 and PIC18(L)F46K22 only.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 — ...

  • Page 110

    ... PIC18(L)F2X/4XK22 NOTES: DS41412D-page 110 Preliminary  2010 Microchip Technology Inc. ...

  • Page 111

    ... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 ...

  • Page 112

    ... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H  2010 Microchip Technology Inc. ...

  • Page 113

    ... GIE/GIEH bit of the INTCON register is the global interrupt enable which enables all non-peripheral interrupt sources and disables all interrupt sources, including the peripherals. All interrupts branch to address 0008h in Compatibility mode.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 9.2 Interrupt Priority The interrupt priority feature is enabled by setting the IPEN bit of the RCON register ...

  • Page 114

    ... INT2IE INT2IP IPEN IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP (1) RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary  2010 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEH/GIE GIEL/PEIE ...

  • Page 115

    ... A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared port change interrupts also require the individual pin IOCB enables.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Note: Interrupt flag bits are set when an interrupt ...

  • Page 116

    ... This feature allows for software polling. DS41412D-page 116 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RBIP bit Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 117

    ... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-0 R/W-0 U-0 INT2IE INT1IE — ...

  • Page 118

    ... R-0 R/W-0 R/W-0 TX1IF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 119

    ... A TMR1 register capture occurred (must be cleared by software TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared by software TMR1 register compare match occurred PWM mode: Unused in this mode.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-0 R/W-0 R/W-0 EEIF BCL1IF HLVDIF U = Unimplemented bit, read as ‘ ...

  • Page 120

    ... TMR gate interrupt occurred (must be cleared in software TMR gate occurred DS41412D-page 120 R/W-0 R/W-0 R/W-0 TX2IF CTMUIF TMR5GIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR3GIF TMR1GIF bit Bit is unknown 2 C master was transmitting  2010 Microchip Technology Inc. ...

  • Page 121

    ... A TMR register capture occurred (must be cleared in software TMR register capture occurred Compare mode TMR register compare match occurred (must be cleared in software TMR register compare match occurred PWM mode: Unused in PWM mode.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 U-0 U-0 R/W-0 — — ...

  • Page 122

    ... TMR4 to PR4 match occurred (must be cleared in software TMR4 to PR4 match occurred DS41412D-page 122 U-0 U-0 R/W-0 — — TMR6IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2010 Microchip Technology Inc. R/W-0 R/W-0 TMR5IF TMR4IF bit Bit is unknown ...

  • Page 123

    ... TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘ ...

  • Page 124

    ... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS41412D-page 124 R/W-0 R/W-0 R/W-0 EEIE BCL1IE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 125

    ... Enabled 0 = Disabled bit 1 TMR3GIE: TMR3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1GIE: TMR1 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-0 R/W-0 R/W-0 TX2IE CTMUIE TMR5GIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

  • Page 126

    ... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 R/W-0 — — TMR6IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2010 Microchip Technology Inc. R/W-0 R/W-0 CCP4IE CCP3IE bit Bit is unknown R/W-0 R/W-0 TMR5IE TMR4IE ...

  • Page 127

    ... Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ...

  • Page 128

    ... Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority DS41412D-page 128 R/W-1 R/W-1 R/W-1 EEIP BCL1IP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR3IP CCP2IP bit Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 129

    ... Low priority bit 1 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-0 R/W-0 R/W-0 TX2IP CTMUIP TMR5GIP U = Unimplemented bit, read as ‘0’ ...

  • Page 130

    ... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 R/W-0 — — TMR6IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2010 Microchip Technology Inc. R/W-0 R/W-0 CCP4IP CCP3IP bit Bit is unknown R/W-0 R/W-0 TMR5IP TMR4IP ...

  • Page 131

    ... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 9.9 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh  00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE of the INTCON register ...

  • Page 132

    ... CCP4IE CCP3IE 126 TMR5IE TMR4IE 126 TMR2IF TMR1IF 118 TMR3IF CCP2IF 119 TMR1GIF 120 CCP4IF CCP3IF 121 TMR5IF TMR4IF 122 RB1 RB0 151 POR BOR 60 Register Bit 1 Bit 0 on Page PBADEN CCP2MX 354 — STRVEN 355  2010 Microchip Technology Inc. ...

  • Page 133

    ... Port Note 1: I/O pins have diode protection to V  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 10.1 PORTA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i ...

  • Page 134

    ... LATA<5> data output; not affected by analog input TTL PORTA<5> data input; disabled when analog input 0 enabled. O DIG Comparator C2 output DIG SR Latch Q output TTL SPI slave select input (MSSP1 High/Low-Voltage Detect input A/D input 4. 1 Preliminary Description Schmitt Trigger input  2010 Microchip Technology Inc. ...

  • Page 135

    ... TABLE 10-3: CONFIGURATION REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 CONFIG1H IESO FCMEN PRICLKEN PLLCFG Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 ANSEL Pin Buffer Setting Type Type — O DIG LATA< ...

  • Page 136

    ... CCP2 SCK1 (6) P2A RC3 RB3 (1) P1D SDA1 RB4 RC4 Preliminary (2) (2) PORTD PORTE (8) SCL2 CCP3 (8) SCK2 P3A RD0 RE0 SDA2 P3B CCP4 RE1 RD1 P2B CCP5 (4) RD2 RE2 P2C MCLR RD3 V PP RE3 SDO2 P2D RD4  2010 Microchip Technology Inc. ...

  • Page 137

    ... Function default pin. 4: Function default pin (28-pin devices). 5: Function default pin (40/44-pin devices). 6: Function alternate pin. 7: Function alternate pin (28-pin devices). 8: Function alternate pin (40/44-pin devices)  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Port Function Priority by Port Pin PORTB PORTC (3) CCP3 SDO1 (3) P3A RC5 ...

  • Page 138

    ... Any read or write of PORTB to clear the mis- match condition (except when PORTB is the source or destination of a MOVFF instruction). b) Execute at least one instruction after reading or writing PORTB, then clear the flag bit, RBIF. Preliminary  2010 Microchip Technology Inc. which also have their ...

  • Page 139

    ... Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. 3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 10.3.3 ALTERNATE FUNCTIONS PORTB is multiplexed with several peripheral functions (Table 10-5) ...

  • Page 140

    ... Interrupt-on-change pin DIG Enhanced CCP2 PWM output DIG Enhanced CCP3 PWM output DIG Compare 3 output/PWM 3 output Capture 3 input Timer3 clock input Timer1 external clock gate input Analog input 13. 1 Preliminary Description Schmitt Trigger input with I C.  2010 Microchip Technology Inc. ...

  • Page 141

    ... T5GPOL TRISB TRISB7 TRISB6 WPUB WPUB7 WPUB6 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB. Note 1: Available on PIC18(L)F4XK22 devices.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 ANSEL Pin Buffer Setting Type Type — O DIG LATB<6> data output; not affected by analog input. ...

  • Page 142

    ... Initialize PORTC by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs ; Value used to ; enable digital inputs ; No ANSEL bits for RC<1:0> ; RC<7:6> dig input enable  2010 Microchip Technology Inc. ...

  • Page 143

    ... Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. 3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 ANSEL Pin Buffer setting Type Type — ...

  • Page 144

    ... PORTC<7> data input; disabled when analog input 1 0 enabled. O CMOS Enhanced CCP3 PWM output EUSART 1 asynchronous receive data in DIG EUSART 1 synchronous serial data output EUSART 1 synchronous serial data input Analog input 19 Preliminary Description Schmitt Trigger input with I C.  2010 Microchip Technology Inc. ...

  • Page 145

    ... TABLE 10-10: CONFIGURATION REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 CONFIG3H MCLRE — Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Bit 5 Bit 4 Bit 3 ANSC5 ANSC4 ANSC3 PSS1AC<1:0> DC1B<1:0> ...

  • Page 146

    ... SR Latch inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when Analog mode with the priority shown below. Preliminary  2010 Microchip Technology Inc. ...

  • Page 147

    ... AN = Analog input or output; TTL = TTL compatible input High Voltage Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output Schmitt Trigger input with CMOS levels; I Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 ANSEL Pin Buffer ...

  • Page 148

    ... Schmitt Trigger input with I C. Register on Bit 1 Bit 0 Page ANSD1 ANSD0 153 WUE ABDEN 274 201 201 201 LATD1 LATD0 155 RD1 RD0 151 OERR RX9D 273 SLRB SLRA 156 256 TRISD1 TRISD0 154 Register Bit 1 Bit 0 on Page 354  2010 Microchip Technology Inc. ...

  • Page 149

    ... Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<0> as input ; RE<1> as output ; RE<2> as input  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 10.6.2 PORTE ON 28-PIN DEVICES For PIC18F2XK22 devices, PORTE is only available when Master Clear (MCLR = 0). In these cases, PORTE is a single bit, input only port comprised of RE3 only ...

  • Page 150

    ... TRISE2 Preliminary Description Schmitt Trigger input with I C. Reset Bit 1 Bit 0 Values on page ANSE1 ANSE0 154 — RBIP 116 LATE1 LATE0 155 (1) (1) (1) RE1 RE0 152 SLRB SLRA 156 (1) (1) (1) TRISE1 TRISE0 154  2010 Microchip Technology Inc. ...

  • Page 151

    ... Rx<7:0>: PORTx I/O bit values Note 1: Register Description for PORTA, PORTB, PORTC and PORTD. 2: Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Bit 5 Bit 4 Bit 3 Bit 2 P2BMX ...

  • Page 152

    ... U = Unimplemented bit, read as ‘0’ Bit is unknown (1) (2), (3) U-0 R/W-1 R/W-1 — ANSA3 ANSA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-u/x R/W-u/x (2), (3) (2), (3) RE1 RE0 bit 0 R/W-1 R/W-1 ANSA1 ANSA0 bit Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 153

    ... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ANSD<7:0>: RD<7:0> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-1 R/W-1 R/W-1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ ...

  • Page 154

    ... TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-1 R/W-1 (1) (1) ANSE1 ANSE0 bit Bit is unknown R/W-1 R/W-1 TRISx1 TRISx0 bit Bit is unknown R/W-1 R/W-1 (1) (1) TRISE1 TRISE0 bit Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 155

    ... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled on PORT pin 0 = Pull-up disabled on PORT pin  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 (1) R/W-x/u R/W-x/u R/W-x/u LATx4 LATx3 LATx2 U = Unimplemented bit, read as ‘0’ ...

  • Page 156

    ... Bit is cleared (1) R/W-1 R/W-1 R/W-1 (1) (1) SLRE SLRD SLRC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (2) Preliminary U-0 U-0 — — bit Bit is unknown R/W-1 R/W-1 SLRB SLRA bit Bit is unknown  2010 Microchip Technology Inc. ...

  • Page 157

    ... Microchip Technology Inc. PIC18(L)F2X/4XK22 The T0CON register aspects of the module’s operation, including the prescale selection both readable and writable. ...

  • Page 158

    ... TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. ). OSC 1 Sync with Internal Clocks Programmable 0 Prescaler (2 T Delay Preliminary Figure 11-2). TMR0H is updated with Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus  2010 Microchip Technology Inc. ...

  • Page 159

    ... GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 T0CON TMR0ON T08BIT TMR0H TMR0L TRISA TRISA7 TRISA6 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer0.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 1 Sync with Internal TMR0L Clocks Delay 11.3.1 ...

  • Page 160

    ... PIC18(L)F2X/4XK22 NOTES: DS41412D-page 160 Preliminary  2010 Microchip Technology Inc. ...

  • Page 161

    ... T3CKI is not available when the secondary oscillator is enabled, unless T3CMX = 1. 7: Synchronized comparator output should not be used in conjunction with synchronized TxCKI.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 • Special Event Trigger (with CCP/ECCP) • Selectable Gate Source Polarity • Gate Toggle Mode • ...

  • Page 162

    ... Timer1/3/5 is disabled (TMRxON = 0) when TxCKI is high then Timer1/3/5 is enabled (TMRxON=1) when TxCKI is low. TxSOSCEN System Clock ( OSC Instruction Clock (F x OSC External Clocking on TxCKI Pin 0 Osc.Circuit On SOSCI/SOSCO Pins 1 Preliminary internal clock source is selected, the Clock Source /4)  2010 Microchip Technology Inc. ...

  • Page 163

    ... Note: When switching from synchronous to asynchronous operation possible to skip an increment. When switching from asynchronous to synchronous operation possible to produce an additional increment.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 12.5.1 READING AND WRITING TIMER1/3/5 IN ASYNCHRONOUS COUNTER MODE Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...

  • Page 164

    ... GATE RESOURCES FOR TIMER2/4/6 MATCH TO PR2/4/6 Timer1/3/5 Gate Match Selection TMR2 Match to PR2 TMR4 Match to PR4 TMR6 Match to PR6 TxG Pin Gate Operation Timer2/4/6 Match Gate Operation Section 12.7.2 “Timer1/3/5 Gate for more information.  2010 Microchip Technology Inc. ...

  • Page 165

    ... Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 12.7.4 TIMER1/3/5 GATE SINGLE-PULSE MODE When Timer1/3/5 Gate Single-Pulse mode is enabled possible to capture a single-pulse gate event. ...

  • Page 166

    ... In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 17.2.8 “Special Event Trigger”. Preliminary  2010 Microchip Technology Inc. see Section 14.0 period register for ...

  • Page 167

    ... Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 12-4: TIMER1/3/5 GATE ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3/5 N  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Preliminary DS41412D-page 167 ...

  • Page 168

    ... TIMER1/3/5 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5 N Cleared by software TMRxGIF DS41412D-page 168 Cleared by hardware on falling edge of TxGVAL Set by hardware on falling edge of TxGVAL Preliminary  2010 Microchip Technology Inc Cleared by software ...

  • Page 169

    ... Reset and disconnects the module’s clock source. The Module Disable bits for Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5 (TMR5MD) are in the PMD0 Register. See “Power-Managed Modes” for more information.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 ...

  • Page 170

    ... Enables Timer1/3 Stops Timer1/3/5 Clears Timer1/3/5 Gate flip-flop DS41412D-page 170 R/W-0/u R/W-0/u R/W-0/u TxSOSCEN TxSYNC U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ) OSC /4) OSC ) OSC Preliminary R/W-0/0 R/W-0/u TxRD16 TMRxON bit 0  2010 Microchip Technology Inc. ...

  • Page 171

    ... Unaffected by Timer1/3/5 Gate Enable (TMRxGE). bit 1-0 TxGSS<1:0>: Timer1/3/5 Gate Source Select bits 00 = Timer1/3/5 Gate pin 01 = Timer2/4/6 Match PR2/4/6 output (See 10 = Comparator 1 optionally synchronized output (SYNCC1OUT Comparator 2 optionally synchronized output (SYNCC2OUT)  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-0/u R/W/HC-0/u R-x/x TxGSPM TxGGO/DONE TxGVAL U = Unimplemented bit, read as ‘ ...

  • Page 172

    ... TMR5IF TMR4IF 122 TMR2MD TMR1MD 56 T1RD16 TMR1ON 170 T1GSS<1:0> 171 T3RD16 TMR3ON 170 T3GSS 171 T5RD16 TMR5ON 170 T5GSS 171 — — TRISB1 TRISB0 154 TRISC1 TRISC0 154 Reset Bit 1 Bit 0 Values on Page PBADEN CCP2MX 354  2010 Microchip Technology Inc. ...

  • Page 173

    ... Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 13-1 for a block diagram of Timer2/4/6. FIGURE 13-1: TIMER2/4/6 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16 2 TxCKPS<1:0>  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 TMRx Output Reset TMRx Postscaler Comparator 1 PRx TxOUTPS<3:0> Preliminary ...

  • Page 174

    ... The Module Disable bits for Timer2 (TMR2MD), Timer4 (TMR4MD) and Timer6 (TMR6MD) are in the PMD0 Register. See “Power-Managed Modes” Preliminary the input for the 4-bit module is selected using the Section 3.0 for more information.  2010 Microchip Technology Inc. ...

  • Page 175

    ... TMRxON: TimerX On bit 1 = TimerX TimerX is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 R/W-0 R/W-0 R/W-0 TMRxON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

  • Page 176

    ... C4TSEL<1:0> 204 INT0IF RBIF 115 TMR2IP TMR1IP 127 TMR5IP TMR4IP 130 TMR2IE TMR1IE 123 TMR5IE TMR4IE 126 TMR2IF TMR1IF 118 TMR5IF TMR4IF 122 TMR1MD 56 — — — T2CKPS<1:0> 170 T4CKPS<1:0> 170 T6CKPS<1:0> 170 — — —  2010 Microchip Technology Inc. ...

  • Page 177

    ... PIC18(L)F43K22 PIC18(L)F44K22 Enhanced PWM PIC18(L)F45K22 Full-Bridge PIC18(L)F46K22  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Note 1: In devices with more than one CCP module very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules ...

  • Page 178

    ... OSC Preliminary CCPRxH CCPRxL Capture Enable TMR1/3/5H TMR1/3/5L the CCP output pin Register 24-4 for more details. PIC18(L)F4XK22 I/O pin RB3 RC1 RE0 RB5 ) should not be OSC  2010 Microchip Technology Inc. ...

  • Page 179

    ... ADIE Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 14.1.5 CAPTURE DURING SLEEP Capture mode requires a 16-bit TimerX module for use as a time base. There are four options for driving the 16-bit TimerX module in Capture mode ...

  • Page 180

    ... T5GSS 171 — — — — — — TRISA2 TRISA1 TRISA0 154 TRISB2 TRISB1 TRISB0 154 TRISC2 TRISC1 TRISC0 154 TRISD2 TRISD1 TRISD0 154 (1) (1) (1) TRISE1 TRISE0 154 Register Bit 1 Bit 0 on Page PBADEN CCP2MX 354  2010 Microchip Technology Inc. ...

  • Page 181

    ... TimerX Interrupt Flag, (TMRxIF) is not set Additional Function on • CCP5 will - Set ADCON0<1>, GO/DONE bit to start an ADC Conversion if ADCON<0>, ADON = 1.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 14.2.1 CCP PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the associated TRIS bit. ...

  • Page 182

    ... OSC Register Bit 2 Bit 1 Bit 0 on Page CCP1M<3:0> 201 CCP2M<3:0> 201 CCP3M<3:0> 201 CCP4M<3:0> 201 CCP5M<3:0> 201 — — — — — — — — — — — C1TSEL<1:0> 204 C4TSEL<1:0> 204 TMR0IF INT0IF RBIF 115  2010 Microchip Technology Inc. ...

  • Page 183

    ... CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 CONFIG3H MCLRE — P2BMX Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Bit 5 Bit 4 Bit 3 RC1IP TX1IP SSP1IP C2IP EEIP BCL1IP — ...

  • Page 184

    ... Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. 5. Load the CCPRxL register and the DCxB<1:0> bits of the CCPxCON register, with the PWM duty cycle value. Preliminary  2010 Microchip Technology Inc. TMRx = PRx CCPxCON<5:4> CCPx TRIS ...

  • Page 185

    ... The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: The Timer postscaler (see “Timer2/4/6 Module”) is not used in the determination of the PWM frequency.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 14.3.5 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit below. value to multiple registers: CCPRxL register and DCxB< ...

  • Page 186

    ... PRx + 1 ----------------------------------------- - bits 2   log = 32 MHz) 250 kHz 333.3 kHz 1 1 0x1F 0x17 7 6 MHz) 156.3 kHz 208.3 kHz 1 1 0x1F 0x17 7 6 MHz) 153.85 kHz 200.0 kHz 1 1 0x0C 0x09 5 5  2010 Microchip Technology Inc. ...

  • Page 187

    ... TABLE 14-11: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 CONFIG3H MCLRE — P2BMX Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Bit 5 Bit 4 Bit 3 DC1B<1:0> DC2B<1:0> DC3B<1:0> DC4B<1:0> ...

  • Page 188

    ... ECCP module waits until the start of a new PWM period before generating a PWM signal. PxM<1:0> CCPxM<3:0> CCPx/PxA TRISx PxB TRISx Output Q Controller PxC TRISx PxD TRISx PWMxCON Preliminary the generation of an CCPx/PxA PxB (2) PxC (2) PxD  2010 Microchip Technology Inc. ...

  • Page 189

    ... Prescale Value) OSC • Pulse Width = T * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) OSC • Delay = (PWMxCON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWMxCON register Mode”).  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 CCPx/PxA PxB (1) (1) Yes Yes Yes Yes Yes ...

  • Page 190

    ... Pulse Width = T * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) OSC • Delay = (PWMxCON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWMxCON register Mode”). DS41412D-page 190 Pulse 0 Width Period (1) (1) Delay Delay (Section 14.4.5 “Programmable Dead-Band Delay Preliminary  2010 Microchip Technology Inc. PRx+1 ...

  • Page 191

    ... Standard Half-Bridge Circuit (“Push-Pull”) Half-Bridge Output Driving a Full-Bridge Circuit PxA PxB  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure PxA and PxB as outputs. ...

  • Page 192

    ... PORT data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs. FIGURE 14-10: EXAMPLE OF FULL-BRIDGE APPLICATION PxA PxB PxC PxD DS41412D-page 192 Figure 14-11 FET Driver Load FET Driver QB V- Preliminary QC FET Driver FET Driver QD  2010 Microchip Technology Inc. ...

  • Page 193

    ... Forward Mode (2) PxA Pulse Width (2) PxB (2) PxC (2) PxD (1) Reverse Mode Pulse Width (2) PxA (2) PxB (2) PxC (2) PxD (1) Note 1: At this time, the TMRx register is equal to the PRx register. 2: Output signal is shown as active-high.  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Period (1) Period (1) Preliminary DS41412D-page 193 ...

  • Page 194

    ... Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. (1) Period Pulse Width (2) Preliminary Period , OSC  2010 Microchip Technology Inc. ...

  • Page 195

    ... Section 14.4.4 “Auto-Restart The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD]. The state  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 Forward Period each pin pair is determined by the PSSxAC< ...

  • Page 196

    ... Missing Pulse Missing Pulse (Auto-Shutdown) (CCPxASE not clear) Timer Timer Overflow Overflow Overflow Shutdown Event Occurs Shutdown CCPxASE Event Clears Cleared by Preliminary Timer Timer Overflow PWM Resumes CCPxASE Cleared by Firmware Timer Timer Overflow PWM Resumes Hardware  2010 Microchip Technology Inc. ...

  • Page 197

    ... The lower seven bits of the associated PWMxCON register (Register 14-6) sets the delay period in terms of microcontroller instruction cycles (T CY FIGURE 14-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”)  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 14-16: Pulse Width (2) PxA td (2) PxB ...

  • Page 198

    ... Figures 14-19 of the PWM steering depending on the STRxSYNC setting. Preliminary SIMPLIFIED STEERING BLOCK DIAGRAM PxA pin 1 0 TRIS PxB pin 1 0 TRIS PxC pin 1 0 TRIS PxD pin 1 0 TRIS and 14-20 illustrate the timing diagrams  2010 Microchip Technology Inc. ...

  • Page 199

    ... PWM STRx P1<D:A> PORT Data  2010 Microchip Technology Inc. PIC18(L)F2X/4XK22 modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMRxIF bit of the PIR1, PIR2 or PIR5 register being set as the second PWM period begins ...

  • Page 200

    ... STR1A 206 STR2B STR2A 206 STR3B STR3A 206 206 206 206 T2CKPS<1:0> 170 T4CKPS<1:0> 170 T6CKPS<1:0> 170 — — — TRISA1 TRISA0 154 TRISB1 TRISB0 154 TRISC1 TRISC0 154 TRISD1 TRISD0 154 (1) (1) (1) TRISE1 TRISE0 154  2010 Microchip Technology Inc. ...