PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 41

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PIC18F45K22-I/P

Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45K22-I/P

A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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TABLE 2-3:
2.9
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS<1:0>) bits of the
OSCCON register.
PIC18(L)F2X/4XK22 devices contain circuitry to pre-
vent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
2.9.1
The System Clock Select (SCS<1:0>) bits of the
OSCCON register select the system clock source that
is used for the CPU and peripherals.
• When SCS<1:0> = 00, the system clock source is
• When SCS<1:0> = 10, the system clock source is
• When SCS<1:0> = 01, the system clock source is
 2010 Microchip Technology Inc.
RC, INTOSC with CLKOUT Floating, external resistor should pull high
RC with IO
INTOSC with IO
EC with IO
EC with CLKOUT
LP, XT, HS
Note:
determined by configuration of the FOSC<3:0>
bits in the CONFIG1H Configuration register.
chosen by the internal oscillator frequency
selected by the INTSRC bit of the OSCTUNE
register, the MFIOSEL bit of the OSCCON2
register and the IRCF<2:0> bits of the OSCCON
register.
the 32.768 kHz secondary oscillator shared with
Timer1, Timer3 and Timer5.
OSC Mode
Clock Switching
See
SYSTEM CLOCK SELECT
(SCS<1:0>) BITS
Table 4-2
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
Floating, external resistor should pull high
Configured as PORTA, bit 7
Floating, pulled by external clock
Feedback inverter disabled at quiescent
voltage level
Floating, pulled by external clock
OSC1 Pin
Preliminary
After a Reset, the SCS<1:0> bits of the OSCCON
register are always cleared.
2.9.2
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<3:0> bits in the CONFIG1H
Configuration register, or from the internal clock
source. In particular, when the primary oscillator is the
source of the primary clock, OSTS indicates that the
Oscillator Start-up Timer (OST) has timed out for LP,
XT or HS modes.
Note:
PIC18(L)F2X/4XK22
Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-
Safe Clock Monitor, does not update the
SCS<1:0> bits of the OSCCON register.
The user can monitor the SOSCRUN,
MFIOFS
OSCCON2 register, and the HFIOFS and
OSTS bits of the OSCCON register to
determine the current system clock source.
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
At logic low (clock/4 output)
Configured as PORTA, bit 6
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
and
OSC2 Pin
LFIOFS
DS41412D-page 41
bits
of
the

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