PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 103

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PIC18F45K22-I/P

Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45K22-I/P

A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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EXAMPLE 6-3:
6.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the WRERR bit will be set
which the user can check to decide whether a rewrite
of the location(s) is needed.
TABLE 6-2:
 2010 Microchip Technology Inc.
TBLPTRU
TBPLTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
PROGRAM_MEMORY
Name
Required
Sequence
— = unimplemented, read as ‘0’. Shaded bits are not used during Flash/EEPROM access.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
GIE/GIEH
OSCFIP
OSCFIF
OSCFIE
EEPGD
Bit 7
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
DECFSZ
BRA
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DCFSZ
BRA
BSF
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PEIE/GIEL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
CFGS
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Bit 6
C1IP
C1IF
C1IE
EEPROM Control Register 2 (not a physical register)
COUNTER
WRITE_WORD_TO_HREGS
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
COUNTER2
WRITE_BYTE_TO_HREGS
INTCON, GIE
EECON1, WREN
TMR0IE
Bit 5
C2IP
C2IF
C2IE
Program Memory Table Pointer Upper Byte (TBLPTR<21:16>)
Program Memory Table Latch
INT0IE
FREE
EEIP
EEIF
EEIE
Bit 4
Preliminary
; loop until holding registers are full
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; repeat for remaining write blocks
;
; re-enable interrupts
; disable write to memory
WRERR
BCLIP
BCLIF
BCLIE
RBIE
Bit 3
6.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See
CPU”
6.6
See
Protection”
program memory.
PIC18(L)F2X/4XK22
Section 24.3 “Program Verification and Code
for more detail.
TMR0IF
Flash Program Operation During
Code Protection
HLVDIP
HLVDIF
HLVDIE
WREN
Bit 2
PROTECTION AGAINST
SPURIOUS WRITES
for details on code protection of Flash
Section 24.0 “Special Features of the
TMR3IP
TMR3IF
TMR3IE
INT0IF
Bit 1
WR
CCP2IP
CCP2IF
CCP2IE
Bit 0
RBIF
DS41412D-page 103
RD
Values on
Reset
page
128
124
115
119
97

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