PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 228

• Manufacturer Part Number: PIC18F45K22-I/P
• Description: 40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45K22-I/P

• A/d Inputs: 28-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18(L)F2X/4XK22
15.5.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
Following the ACK, slave hardware clears the CKP bit
and the SCLx pin is held low (see
“Clock Stretching”
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
The transmit data must be loaded into the SSPxBUF
register which also loads the SSPxSR register. Then
the SCLx pin should be released by setting the CKP bit
of the SSPxCON1 register. The eight data bits are
shifted out on the falling edge of the SCLx input. This
ensures that the SDAx signal is valid during the SCLx
high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCLx input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes Idle and waits for
another occurrence of the Start bit. If the SDAx line was
low (ACK), the next transmit data must be loaded into
the SSPxBUF register. Again, the SCLx pin must be
released by setting bit CKP.
An MSSPx interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared by software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
15.5.3.1
A slave receives a Read request and begins shifting
data out on the SDAx line. If a bus collision is detected
and the SBCDE bit of the SSPxCON3 register is set,
the BCLxIF bit of the PIRx register is set. Once a bus
collision is detected, the slave goes Idle and waits to be
addressed again. User software can use the BCLxIF bit
to handle a slave bus collision.
DS41412D-page 228
SLAVE TRANSMISSION
Slave Mode Bus Collision
for more detail). By stretching the
Section 15.5.6
Preliminary
15.5.3.2
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to do
to accomplish a standard transmission.
can be used as a reference to this list.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. SSPxIF is set after the ACK response from the
11. SSPxIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
13. Steps 9-13 are repeated for each transmitted
14. If the master sends a not ACK; the clock is not
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
Note 1: If the master ACKs the clock will be
Master sends a Start condition on SDAx and
SCLx.
S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
Matching address with R/W bit set is received by
the slave setting SSPxIF bit.
Slave hardware generates an ACK and sets
SSPxIF.
SSPxIF bit is cleared by user.
Software reads the received address from
SSPxBUF, clearing BF.
R/W is set so CKP was automatically cleared
after the ACK.
The slave software loads the transmit data into
SSPxBUF.
CKP bit is set releasing SCLx, allowing the mas-
ter to clock the data out of the slave.
master is loaded into the ACKSTAT register.
see if the master wants to clock out more data.
byte.
held, but SSPxIF is still set.
2: ACKSTAT is the only bit updated on the
stretched.
rising edge of SCLx (9th) rather than the
falling.
7-bit Transmission
 2010 Microchip Technology Inc.
Figure 15-17