PIC18F45K22-I/P Microchip Technology Inc., PIC18F45K22-I/P Datasheet - Page 230

no-image

PIC18F45K22-I/P

Manufacturer Part Number
PIC18F45K22-I/P
Description
40 PDIP .600in TUBE, 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45K22-I/P

A/d Inputs
28-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F45K22-I/P
Manufacturer:
MICROCHIP
Quantity:
3 400
Part Number:
PIC18F45K22-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC18F45K22-I/PT
Manufacturer:
SST
Quantity:
3 400
Part Number:
PIC18F45K22-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F45K22-I/PT
Manufacturer:
MIC
Quantity:
20 000
Part Number:
PIC18F45K22-I/PT
0
Company:
Part Number:
PIC18F45K22-I/PT
Quantity:
20 400
PIC18(L)F2X/4XK22
15.5.3.3
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the 8th falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
Figure 15-18
Address Slave Transmission with AHEN enabled.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave hardware automatically clears the CKP bit
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
15. Slave hardware copies the ACK value into the
16. Steps 10-15 are repeated for each byte
17. If the master sends a not ACK the slave
DS41412D-page 230
Note: SSPxBUF cannot be loaded until after the
Note: Master must send a not ACK on the last byte
Bus starts Idle.
Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
Master sends matching address with R/W bit
set. After the 8th falling edge of the SCLx line
the CKP bit is cleared and SSPxIF interrupt is
generated.
Slave software clears SSPxIF.
Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
Slave reads the address value from the SSPxBUF
register clearing the BF bit.
Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSPxCON2 register accordingly.
Slave sets the CKP bit releasing SCLx.
Master clocks in the ACK value from the slave.
and sets SSPxIF after the ACK if the R/W bit is
set.
SSPxBUF setting the BF bit.
sends an ACK value on the 9th SCLx pulse.
ACKSTAT bit of the SSPxCON2 register.
transmitted to the master from the slave.
releases the bus allowing the master to send a
Stop and end the communication.
ACK.
to ensure that the slave releases the SCLx
line to receive a Stop.
7-bit Transmission with Address
Hold Enabled
displays a standard waveform of a 7-bit
Preliminary
 2010 Microchip Technology Inc.

Related parts for PIC18F45K22-I/P