mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 116

• Manufacturer Part Number: mc68hc708mp16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
8.5.8 CGM CPU Interrupt (CGMINT)
8.6 CGM Registers
Technical Data
116
CGMINT is the interrupt signal generated by the PLL lock detector.
The following registers control and monitor operation of the CGM:
Figure 8-4
NOTES:
$FE0B
$FE0C
$FE0D
PBWC
Read:
Read:
Read:
Write:
Write:
Write:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PCTL
PPG
•
•
•
PLL control register (PCTL) (See
PLL bandwidth control register (PBWC) (See
Bandwidth Control
PLL programming register (PPG) ((See
Register.)
PLLIE
AUTO
MUL7
Bit 7
Bit 7
Bit 7
Clock Generator Module (CGM)
is a summary of the CGM registers.
Figure 8-4. CGM I/O Register Summary
= Unimplemented
LOCK
MUL6
PLLF
6
6
6
PLLON
MUL5
ACQ
5
5
5
Register.)
MUL4
BCS
XLD
4
4
4
8.6.1 PLL Control
VRS7
3
1
3
0
3
8.6.3 PLL Programming
MC68HC708MP16
VRS6
Freescale Semiconductor
2
1
2
0
2
8.6.2 PLL
VRS5
1
1
1
0
1
Register.)
—
Rev. 3.1
VRS4
Bit 0
Bit 0
Bit 0
1
0