mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 80

• Manufacturer Part Number: mc68hc708mp16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

N O N - D I S C L O S U R E
INH Inherent
IMM Immediate
DIR Direct
EXT Extended
DD
IX+D Indexed-Direct
*
LSB
Pre-byte for stack pointer indexed instructions
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MSB
Direct-Direct
BRSET0
3
BRCLR0
3
BRSET1
3
BRCLR1
3
BRSET2
3
BRCLR2
3
BRSET3
3
BRCLR3
3
BRSET4
3
BRCLR4
3
BRSET5
3
BRCLR5
3
BRSET6
3
BRCLR6
3
BRSET7
3
BRCLR7
3
Bit Manipulation
DIR
0
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCLR0
BCLR1
BCLR2
BCLR3
BCLR4
BCLR5
BCLR6
BCLR7
BSET0
BSET1
BSET2
BSET3
BSET4
BSET5
BSET6
BSET7
DIR
REL Relative
IX
IX1
IX2
IMD Immediate-Direct
DIX+ Direct-Indexed
1
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Branch
BHCC
BHCS
BMC
REL
BRA
BRN
BCC
BCS
BNE
BEQ
BMS
BLS
BPL
BMI
BHI
BIL
BIH
2
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
3
2
2
2
2
2
2
2
2
3
2
2
2
CBEQ
STHX
DBNZ
COM
NEG
ROR
DEC
LSR
ASR
ROL
TST
CLR
DIR
LSL
INC
3
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
4
5
4
4
4
4
4
4
4
4
5
4
3
3
1
3
1
1
1
3
1
1
1
1
1
2
1
1
3
1
CBEQA
DBNZA
COMA
NEGA
RORA
ASRA
DECA
LSRA
LDHX
ROLA
CLRA
LSLA
INCA
TSTA
MUL
MOV
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+
IX1+ Indexed, 1-Byte Offset with
INH
4
IMM
IMM
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
DD
1
4
5
1
1
3
1
1
1
1
1
3
1
1
5
1
Indexed, No Offset with
Post Increment
Post Increment
Read-Modify-Write
1
3
1
1
1
2
1
1
1
1
1
2
1
1
2
1
CBEQX
DBNZX
COMX
NEGX
LDHX
RORX
ASRX
ROLX
DECX
CLRX
LSRX
LSLX
TSTX
INCX
MOV
INH
DIV
5
DIX+
IMM
INH
INH
INH
INH
DIR
INH
INH
INH
INH
INH
INH
INH
INH
INH
1
4
7
1
1
4
1
1
1
1
1
3
1
1
4
1
2
3
1
2
2
3
2
2
2
2
2
3
2
2
3
2
CBEQ
CPHX
DBNZ
COM
NEG
ROR
DEC
MOV
NSA
LSR
ASR
ROL
TST
CLR
LSL
INC
IX1
6
IX1+
IMM
IMD
INH
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
4
5
3
4
4
3
4
4
4
4
4
5
4
3
4
3
Table 6-2. Opcode Map
3
4
3
3
3
3
3
3
3
4
3
3
3
CBEQ
DBNZ
COM
NEG
ROR
ASR
ROL
DEC
SP1
9E6
LSR
LSL
TST
CLR
INC
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
A G R E E M E N T
5
6
5
5
5
5
5
5
5
6
5
4
4
1
2
1
1
1
2
1
1
1
1
1
2
1
1
2 IX+D
1
CBEQ
CPHX
DBNZ
NEG
COM
ROR
MOV
DAA
LSR
ASR
ROL
DEC
CLR
LSL
INC
TST
Low Byte of Opcode in Hexadecimal
IX
7
INH
DIR
IX+
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
3
4
2
3
3
4
3
3
3
3
3
4
3
2
4
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PULA
PSHA
PULX
PSHX
PULH
PSHH
CLRH
STOP
WAIT
RTS
SWI
INH
TAP
TPA
RTI
8
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
Control
7
4
9
2
1
2
2
2
2
2
2
1
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
BGE
BGT
CLC
SEC
RSP
NOP
BLE
TXS
TSX
TAX
TXA
INH
BLT
CLI
SEI
9
*
REL
REL
REL
REL
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
3
3
3
3
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
CMP
EOR
ORA
IMM
SUB
SBC
CPX
AND
ADC
ADD
BSR
LDX
LDA
BIT
AIS
AIX
A
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
REL
IMM
IMM
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
LSB
CMP
AND
EOR
ADC
ORA
ADD
SUB
SBC
CPX
LDA
JMP
JSR
LDX
STX
DIR
STA
BIT
B
0
MSB
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
3
3
3
3
3
3
3
3
3
3
3
3
2
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
BRSET0
3
SUB
CMP
SBC
CPX
AND
EOR
ADC
ORA
ADD
EXT
LDA
STA
JMP
JSR
LDX
STX
BIT
C
0
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
DIR
R E Q U I R E D
4
4
4
4
4
4
4
4
4
4
4
4
3
5
4
4
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
High Byte of Opcode in Hexadecimal
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
Register/Memory
CMP
EOR
ORA
SUB
SBC
CPX
AND
ADC
ADD
JMP
LDX
STX
LDA
STA
JSR
IX2
BIT
D
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
4
4
4
4
4
4
4
4
4
4
4
4
4
6
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
CMP
AND
EOR
ADC
ORA
ADD
SP2
9ED
SUB
SBC
CPX
LDA
LDX
STX
STA
BIT
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SUB
CMP
SBC
CPX
AND
EOR
ADC
ORA
ADD
JMP
LDA
STA
JSR
LDX
STX
BIT
IX1
E
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
3
3
3
3
3
3
3
3
3
3
3
3
3
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
CMP
EOR
ORA
SUB
SBC
CPX
AND
ADC
ADD
LDX
STX
SP1
9EE
LDA
STA
BIT
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CMP
AND
EOR
ADC
ORA
ADD
SUB
SBC
CPX
LDA
JMP
JSR
LDX
STX
STA
BIT
IX
F
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2