mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 323

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mc68hc708mp16

Manufacturer Part Number
mc68hc708mp16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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MC68HC708MP16
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NOTE:
Rev. 3.1
DDRB[7:0] — Data Direction Register B Bits
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 15-7
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
the operation of the port B pins.
DDRB
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
Bit
0
1
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
READ DDRB ($0007)
WRITE DDRB ($0007)
WRITE PTB ($0001)
READ PTB ($0001)
PTB Bit
shows the port B I/O logic.
X
X
Input/Output (I/O) Ports
(1)
Table 15-2. Port B Pin Functions
Figure 15-7. Port B I/O Circuit
RESET
I/O Pin Mode
Input, Hi-Z
Output
(2)
DDRBx
PTBx
Accesses to
Read/Write
DDRB[7:0]
DDRB[7:0]
DDRB
Table 15-2
PTB[7:0]
Input/Output (I/O) Ports
Read
Accesses to PTB
Pin
summarizes
Technical Data
PTB[7:0]
PTB[7:0]
Write
PTBx
323
(3)

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