mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 176

• Manufacturer Part Number: mc68hc708mp16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Pulse Width Modulator for Motor Control (PWMMC)
Technical Data
176
NOTE:
NOTE:
The user should initialize the PWM registers and set the LDOK bit before
enabling the PWM.
A PWM CPU interrupt request can still be generated when LDOK is zero.
ISENS1:ISENS0 — Current Sense Correction Bits
PWMF— PWM Reload Flag
When PWMF is cleared, pending PWM CPU interrupts are cleared (not
including fault interrupts).
PWMINT — PWM Interrupt Enable
Pulse Width Modulator for Motor Control (PWMMC)
These read/write bits select the top/bottom correction scheme as
shown in
This read/write bit is set at the beginning of every reload cycle
regardless of the state of the LDOK bit. This bit is cleared by reading
PWM control register 1 with the PWMF flag set, then writing a logic 0
to PWMF. If another reload occurs before the clearing sequence is
complete, then writing logic 0 to PWMF has no effect.
This read/write bit allows the user to enable and disable PWM CPU
interrupts. If set, a CPU interrupt will be pending when the PWMF flag
is set.
Current Correction Bits
1 = New reload cycle began
0 = New reload cycle has not begun
1 = Enable PWM CPU interrupts
0 = Disable PWM CPU interrupts
ISENS1:ISENS0
Table
00
01
10
11
9-8.
Table 9-8. Correction Methods
Bits IPOL1, IPOL2, and IPOL3 used for correction
Current sensing on pins IS1, IS2, and IS3 occurs
Current sensing on pins IS1, IS2, and IS3 occurs
during the dead-time.
at the half cycle in center-aligned mode and at
the end of the cycle in edge-aligned mode.
Correction Method
MC68HC708MP16
Freescale Semiconductor
—
Rev. 3.1