mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 177
mc68hc708mp16
Manufacturer Part Number
mc68hc708mp16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC708MP16.pdf
(398 pages)
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9.11.5 PWM Control Register 2
MC68HC708MP16
Freescale Semiconductor
NOTE:
NOTE:
—
Rev. 3.1
Address:
When PWMINT is cleared, pending CPU interrupts are inhibited.
DISX — Software Disable for Bank X
DISY — Software Disable for Bank Y
PWM control register 2 controls the PWM load frequency, the PWM
correction method, and the PWM counter prescaler. For ease of
software and to avoid erroneous PWM periods, some of these register
bits are buffered. The PWM generator will not use the prescaler value
until the LDOK bit has been set, and a new PWM cycle is starting. The
correction bits are used at the beginning of each PWM cycle (if the
ISENSx bits are configured for software correction). The load frequency
bits are not used until the current load cycle is complete.
The user should initialize this register before enabling the PWM.
Reset:
Read:
Write:
Pulse Width Modulator for Motor Control (PWMMC)
This read/write bit allows the user to disable one or more PWM pins
in bank X. The pins that are disabled are determined by the disable
mapping write-once register.
This read/write bit allows the user to disable one or more PWM pins
in bank Y. The pins that are disabled are determined by the disable
mapping write-once register.
1 = Disable PWM pins in bank X
0 = Re-enable PWM pins at beginning of next PWM cycle
1 = Disable PWM pins in bank Y
0 = Re-enable PWM pins at beginning of next PWM cycle
LDFQ1
$0021
Bit 7
0
Figure 9-44. PWM Control Register 2 (PCTL2)
= Unimplemented
LDFQ0
6
0
0
5
0
Pulse Width Modulator for Motor Control (PWMMC)
IPOL1
0
4
IPOL2
3
0
IPOL3
2
0
PRSC1
1
0
Technical Data
PRSC0
Bit 0
0
177
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