mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 238

• Manufacturer Part Number: mc68hc708mp16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module B (TIMB)
12.7 TIMB During Break Interrupts
12.8 I/O Signals
12.8.1 TIMB Clock Pin (PTE3/TCLKB)
Technical Data
238
A break interrupt stops the TIMB counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See
Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
Port E shares five of its pins with the TIM. PTE3/TCLKB is an external
clock input to the TIMB prescaler. The four TIMB channel I/O pins are
PTE4/TCH0B, PTE5/TCH1B, PTE6/TCH2B, and PTE7/TCH3B.
PTE3/TCLKB is an external clock input that can be the clock source for
the TIMB counter instead of the prescaled internal bus clock. Select the
PTE3/TCLKB input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See
Timer Interface Module B (TIMB)
12.9.1 TIMB Status and Control
7.7.4 SIM Break Flag Control
MC68HC708MP16
Register.)
Freescale Semiconductor
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Rev. 3.1