mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 278

• Manufacturer Part Number: mc68hc708mp16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface Module (SPI)
Technical Data
278
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable
SPTIE— SPI Transmit Interrupt Enable
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
This read/write bit determines the logic state of the SPSCK pin
between transmissions.
data between SPI modules, the SPI modules must have identical
CPOL values. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See
data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module
must be set to logic 1 between bytes. (See
the CPHA bit.
This read/write bit disables the pull-up devices on pins SPSCK,
MOSI, and MISO so that those pins become open-drain outputs.
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. (See
the SPE bit.
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = Master mode
0 = Slave mode
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
Serial Peripheral Interface Module (SPI)
(Figure 13-4
Figure 13-4
13.10 Resetting the
and
and
Figure
Figure
Figure
MC68HC708MP16
Freescale Semiconductor
13-6.) To transmit
13-12.) Reset sets
SPI.) Reset clears
13-6.) To transmit
—
Rev. 3.1