mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 85

• Manufacturer Part Number: mc68hc708mp16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

7.3 SIM Bus Clock Control and Generation
7.3.1 Bus Timing
7.3.2 Clock Start-Up from POR or LVI Reset
MC68HC708MP16
Freescale Semiconductor
OSC1
—
PLL
CGMVCLK
Rev. 3.1
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
from either an external oscillator or from the on-chip PLL. (See
8. Clock Generator Module
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. (See
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this
entire period. The IBUS clocks start upon completion of the timeout.
MONITOR MODE
SELECT
CIRCUIT
CLOCK
USER MODE
BCS
CGM
Figure 7-3. CGM Clock Signals
PTC3
System Integration Module (SIM)
÷
2
Section 8. Clock Generator Module
A
B S*
*When S = 1,
CGMOUT = B
(CGM).)
CGMXCLK
CGMOUT
Figure
System Integration Module (SIM)
7-3. This clock can come
÷
SIM COUNTER
2
SIM
GENERATORS
BUS CLOCK
Technical Data
(CGM).)
Section
85