mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 259
mc68hc708mp16
Manufacturer Part Number
mc68hc708mp16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC708MP16.pdf
(398 pages)
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MC68HC708MP16
Freescale Semiconductor
—
Rev. 3.1
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See
edge is the MSB capture strobe. Therefore the slave must begin driving
its data before the first SPSCK edge, and a falling edge on the SS pin is
used to start the slave data transmission. The slave’s SS pin must be
toggled back to high and then low again between each byte transmitted
as shown in
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
(FOR REFERENCE)
CAPTURE STROBE
MASTER SS
SPSCK (CPOL = 0)
MISO/MOSI
SPSCK (CPOL =1)
(FROM MASTER)
(CPHA = 0)
(CPHA = 1)
SLAVE SS
SLAVE SS
SPSCK CYCLE #
SS (TO SLAVE)
(FROM SLAVE)
Serial Peripheral Interface Module (SPI)
MOSI
MISO
13.8.2 Mode Fault
Figure 13-4. Transmission Format (CPHA = 0)
Figure
MSB
MSB
BYTE 1
Figure 13-5. CPHA/SS Timing
13-5.
1
BIT 6
BIT 6
2
Error.) When CPHA = 0, the first SPSCK
BIT 5
BIT 5
3
BIT 4
BIT 4
BYTE 2
Serial Peripheral Interface Module (SPI)
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
BYTE 3
BIT 1
BIT 1
7
Technical Data
LSB
LSB
8
259
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