mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 348

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mc68hc708mp16

Manufacturer Part Number
mc68hc708mp16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Low-Voltage Inhibit (LVI)
18.4 Functional Description
Technical Data
348
Figure 18-1
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when V
below that level for nine or more consecutive CPU cycles. LVIPWR and
LVIRST are in the configuration register (CONFIG). (See
Configuration Register
MCU remains in reset until V
must be above LVI
reset. (See
comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
DETECTOR
LOW V
V
DD
DD
7.4.2.5 Low-Voltage Inhibit (LVI)
shows the structure of the LVI module. The LVI is enabled
Low-Voltage Inhibit (LVI)
V
V
Figure 18-1. LVI Module Block Diagram
DD
DD
DD
> LVI
< LVI
falls below a voltage, LVI
TRIPR
CPU CLOCK
TRIP
TRIP
= 0
= 1
ANLGTRIP
FROM CONFIG
for only one CPU cycle to bring the MCU out of
LVIPWR
(CONFIG).) Once an LVI reset occurs, the
DD
DIGITAL FILTER
rises above a voltage, LVI
V
DD
FROM CONFIG
LVIOUT
TRIPF
LVIRST
Reset.) The output of the
MC68HC708MP16
, and remains at or
Freescale Semiconductor
Section 5.
TRIPR
LVI RESET
. V
Rev. 3.1
DD
DD

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