mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 122

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mc68hc708mp16

Manufacturer Part Number
mc68hc708mp16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Clock Generator Module (CGM)
Technical Data
122
NOTE:
NOTE:
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS[7:4] — VCO Range Select Bits
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming may result in failure of the PLL to achieve lock.
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency
f
8.6.1 PLL Control
PLLON bit in the PLL control register (PCTL) is set. (See
Special Programming
select bits disables the PLL and clears the BCS bit in the PCTL. (See
8.4.3 Base Clock Selector Circuit
Programming Exceptions
the bits to $6 to give a default range multiply value of 6.
VRS
. (See
MUL7:MUL6:MUL5:MUL4
Clock Generator Module (CGM)
Table 8-1. VCO Frequency Multiplier (N) Selection
8.4.2.1 PLL
0000
0001
0010
0011
1101
1110
1111
Register.) VRS[7:4] cannot be written when the
Circuits,
Exceptions.) A value of $0 in the VCO range
for more information.) Reset initializes
8.4.2.4 Programming the
and
VCO Frequency Multiplier (N)
8.4.2.5 Special
MC68HC708MP16
Freescale Semiconductor
13
14
15
1
1
2
3
8.4.2.5
PLL, and
Rev. 3.1

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