mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 321

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mc68hc708mp16

Manufacturer Part Number
mc68hc708mp16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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MC68HC708MP16
Freescale Semiconductor
NOTE:
Rev. 3.1
DDRA[7:0] — Data Direction Register A Bits
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 15-4
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
the operation of the port A pins.
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
DDRA
Bit
0
1
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
READ DDRA ($0006)
WRITE DDRA ($0006)
WRITE PTA ($0000)
READ PTA ($0000)
shows the port A I/O logic.
PTA Bit
Input/Output (I/O) Ports
X
X
(1)
Table 15-1. Port A Pin Functions
Figure 15-4. Port A I/O Circuit
RESET
Input, Hi-Z
I/O Pin
Output
Mode
(2)
DDRAx
PTAx
Read/Write
DDRA[7:0]
DDRA[7:0]
Accesses
to DDRA
Table 15-1
PTA[7:0]
Read
Accesses to PTA
Input/Output (I/O) Ports
Pin
summarizes
Technical Data
PTA[7:0]
PTA[7:0]
Write
PTAx
(3)
321

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