NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 31

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
5-6 Start Field Bit Definitions ........................................................................................ 119
5-7 Cycle Type Bit Definitions........................................................................................ 120
5-8 Transfer Size Bit Definition ...................................................................................... 120
5-9 SYNC Bit Definition................................................................................................. 121
5-10DMA Transfer Size.................................................................................................. 126
5-11Address Shifting in 16-Bit I/O DMA Transfers ............................................................. 126
5-12Counter Operating Modes........................................................................................ 131
5-13Interrupt Controller Core Connections ....................................................................... 133
5-14Interrupt Status Registers ....................................................................................... 134
5-15Content of Interrupt Vector Byte .............................................................................. 134
5-16APIC Interrupt Mapping .......................................................................................... 140
5-17Interrupt Message Address Format ........................................................................... 142
5-18Interrupt Message Data Format ............................................................................... 143
5-19Stop Frame Explanation .......................................................................................... 144
5-20Data Frame Format ................................................................................................ 145
5-21Configuration Bits Reset by RTCRST# Assertion ......................................................... 148
5-22INIT# Going Active ................................................................................................ 150
5-23NMI Sources.......................................................................................................... 151
5-24DP Signal Differences ............................................................................................. 152
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5-25General Power States for Systems Using Intel
ICH7.................................................. 153
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5-26State Transition Rules for Intel
ICH7 ...................................................................... 155
5-27System Power Plane ............................................................................................... 156
5-28Causes of SMI# and SCI ......................................................................................... 157
5-29Break Events (Mobile/Ultra Mobile Only).................................................................... 160
5-30Sleep Types .......................................................................................................... 163
5-31Causes of Wake Events........................................................................................... 164
5-32GPI Wake Events ................................................................................................... 165
5-33Transitions Due to Power Failure .............................................................................. 166
5-34Transitions Due to Power Button .............................................................................. 167
5-35Transitions Due to RI# Signal .................................................................................. 168
5-36Write Only Registers with Read Paths in ALT Access Mode ........................................... 171
5-37PIC Reserved Bits Return Values .............................................................................. 173
5-38Register Write Accesses in ALT Access Mode .............................................................. 173
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5-39Intel
ICH7 Clock Inputs ........................................................................................ 176
5-40Heartbeat Message Data ......................................................................................... 182
5-41 IDE Transaction Timings (PCI Clocks) ...................................................................... 184
5-42Interrupt/Active Bit Interaction Definition .................................................................. 188
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5-43SATA Features Support in Intel
ICH7 ...................................................................... 191
5-44SATA Feature Description........................................................................................ 192
5-45Legacy Replacement Routing ................................................................................... 198
5-46Bits Maintained in Low Power States ......................................................................... 204
5-47USB Legacy Keyboard State Transitions .................................................................... 205
5-48UHCI vs. EHCI ....................................................................................................... 207
5-49Debug Port Behavior .............................................................................................. 215
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5-50I
C Block Read ...................................................................................................... 223
5-51Enable for SMBALERT# ........................................................................................... 225
5-52Enables for SMBus Slave Write and SMBus Host Events............................................... 225
5-53Enables for the Host Notify Command ....................................................................... 226
5-54Slave Write Registers ............................................................................................. 227
5-55Command Types .................................................................................................... 228
5-56Read Cycle Format ................................................................................................. 229
5-57Data Values for Slave Read Registers........................................................................ 229
5-58Host Notify Format ................................................................................................. 231
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5-59Features Supported by Intel
ICH7 .......................................................................... 232
5-60Output Tag Slot 0 .................................................................................................. 237
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Intel
ICH7 Family Datasheet
31

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