AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 102

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes:
Table 17-3.
Table 17-4.
102
Symbol
SPR0
SPR1
SPDR Address = EAH
Not Bit Addressable
SPSR Address = E8H
Not Bit Addressable
Symbol
SPIF
WCOL
MODF
TXE
Bit
Bit
1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE.
2. Enable the master SPI prior to the slave device.
3. Slave echoes master on the next Tx if not loaded with new data.
AT89LP6440 - Preliminary
SPD7
SPIF
Function
SPI clock rate select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no
effect on the slave. The relationship between SCK and the oscillator frequency, F
SPR1
Function
SPI Transfer Complete Interrupt Flag. When a serial transfer is complete, the SPIF bit is set by hardware and an interrupt
is generated if ESP = 1. The SPIF bit may be cleared by software or by reading the SPI status register followed by
reading/writing the SPI data register.
Write Collision Flag. The WCOL bit is set by hardware if SPDR is written while the transmit buffer is full. The ongoing
transfer is not affected. WCOL may be cleared by software or by reading the SPI status register followed by
reading/writing the SPI data register.
Mode Fault Flag. MODF is set by hardware when a master mode collision is detected (MSTR = 1, SSIG = 0 and SS = 0)
and an interrupt is generated if ESP = 1. MODF must be cleared by software.
Transmit Buffer Empty Flag. Set by hardware when the transmit buffer is loaded into the shift register, allowing a new byte
to be loaded. TXE must be cleared by software. When ENH = 1 and ESP = 1, TXE will generate an interrupt.
7
7
SPDR – SPI Data Register
SPSR – SPI Status Register
0
0
1
1
SPR0
0
1
0
1
WCOL
SPD6
6
6
SCK (TSCK = 0)
f
f
f
f
OSC
OSC
OSC
OSC
/4
/8
/32
/64
MODF
SPD5
5
5
SCK (TSCK = 1)
f
f
f
f
T1OVF
T1OVF
T1OVF
T1OVF
SPD4
TXE
/4
/8
/32
/64
4
4
SPD3
3
–
3
Reset Value = 00H (after cold reset)
unchanged (after warm reset)
SPD2
SSIG
2
2
OSC.
, is as follows:
Reset Value = 0000 X000B
DISSO
SPD1
1
1
SPD0
ENH
0
0
3706A–MICRO–9/09