AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 17

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3-4.
3706A–MICRO–9/09
XSTK
WS[1-0]
EXRAM
ALES
Symbol
CLKREG = 8EH
Not Bit Addressable
Bit
Function
Extended Stack Enable. When XSTK = 0 the stack resides in IDATA and is limited to 256 bytes. Set XSTK = 1 to place
the stack in EDATA for up to 4K bytes of extended stack space. All PUSH, POP, CALL and RET instructions will incur a
one or two cycle penalty when accessing the extended stack.
Wait State Select. Determines the number of wait states inserted into external memory accesses.
WS1
0
0
1
1
External RAM Enable. When EXRAM = 0, MOVX instructions can access the internally mapped portions of the address
space. Accesses to addresses above internally mapped memory will access external memory. Set EXRAM = 1 to
bypass the internal memory and map the entire address space to external memory.
ALE Idle State. When ALES = 0 the idle polarity of ALE is high (active). When ALES = 1 the idle polarity of ALE is low
(inactive). The ALE strobe pulse is always active high. ALES must be zero in order to use P4.4 as a general I/O.
AUXR
–
7
– Auxiliary Control Register
WS0
0
1
0
1
Figure 3-8
an 8-bit paged address. Port 0 serves as a multiplexed address/data bus to the RAM. The ALE
strobe is used to latch the address byte into an external register so that Port 0 can be freed for
data input/output. The Port 2 I/O lines (or other ports) can provide control lines to page the mem-
ory; however, this operation is not handled automatically by hardware. The software application
must change the Port 2 register when appropriate to access different pages. The MOVX @Ri
instructions use Paged Address mode.
Figure 3-8.
Note that prior to using the external memory interface, Port 2, WR (P3.6), RD (P3.7) and ALE
(P4.4) must be configured as outputs. See
is configured automatically to push-pull output mode when outputting address or data and is
–
6
Wait States
0
1
2
3
shows a hardware configuration for accessing 256-byte blocks of external RAM using
External Memory 8-bit Paged Address Mode
–
5
RD / WR Strobe Width
1 x t
2 x t
3 x t
4 x t
CYC
CYC
CYC
CYC
XSTK
P1
RD
WR
4
AT89LP
P3
P2
ALE
P0
WS1
Section 10.1 “Port Configuration” on page
3
I/O
AT89LP6440 - Preliminary
LATCH
PAGE
BITS
WS0
2
DATA
EXTERNAL
MEMORY
WE
ADDR
Reset Value = xxx0 0000B
DATA
EXRAM
OE
1
ALES
0
44. Port 0
17