AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 34

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2
7.3
34
Brown-out Reset
External Reset
AT89LP6440 - Preliminary
meet the minimum system requirements before the device exits reset and starts normal opera-
tion. The RST pin may be held low externally until these conditions are met.
Table 7-1.
The AT89LP6440 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V
during operation by comparing it to a fixed trigger level. The trigger level V
nominally 2.0V. The purpose of the BOD is to ensure that if V
speed, the system will gracefully enter reset without the possibility of errors induced by incorrect
execution. A BOD sequence is shown in
trigger level V
trigger level plus about 200 mV of hysteresis, the start-up timer releases the internal reset after
the specified time-out period has expired
by setting the BOD Enable Fuse.
Figure 7-3.
The AT89LP6440 allows for a wide V
to prevent incorrect execution if V
when a 3.6V supply is coupled with high frequency operation. In such cases an external Brown-
out Reset circuit connected to the RST pin may be required.
The P4.2/RST pin can function as either an active-LOW reset input or as a digital general-
purpose I/O, P4.2. The Reset Pin Enable Fuse, when set to “1”, enables the external reset input
function on P4.2.
used as an input or output pin. When configured as a reset input, the pin must be held low for at
least two clock cycles to trigger the internal reset. The RST pin includes an on-chip pull-up resis-
tor tied to V
SUT Fuse 1
Time-out
Internal
Reset
V
0
0
1
1
DD
DD
. The pull-up is disabled when the pin is configured as P4.2.
BOD
Start-up Timer Settings
Brown-out Detector Reset
V POR
, the internal reset is immediately activated. When V
(See “User Configuration Fuses” on page
SUT Fuse 0
0
1
0
1
(See “User Configuration Fuses” on page
BOD
Clock Source
Internal RC/External Clock
Crystal Oscillator
Internal RC/External Clock
Crystal Oscillator
Internal RC/External Clock
Crystal Oscillator
Internal RC/External Clock
Crystal Oscillator
DD
is lower than the minimum required V
operating range. The on-chip BOD may not be sufficient
Figure
(Table
V BOD
t SUT
7-3. When V
7-1). The Brown-out Detector must be enabled
DD
164.) When cleared, P4.2 may be
DD
decreases to a value below the
fails or dips while executing at
DD
increases above the
164.)
BOD
DD
t
SUT
range, such as
3706A–MICRO–9/09
for the BOD is
16384
(± 5%) µs
1024
2048
1024
4096
4096
512
16
DD
level