AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 31

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2
6.3
6.4
6.5
3706A–MICRO–9/09
External Clock Source
Internal RC Oscillator
System Clock Out
System Clock Divider
The external clock option disables the oscillator amplifier and allows XTAL1 to be driven directly
by an external clock source as shown in
general purpose I/O P4.1, or configured to output a divided version of the system clock.
Figure 6-2.
The AT89LP6440 has an Internal RC oscillator (IRC) tuned to 8.0 MHz ±2.5%. When enabled
as the clock source, XTAL1 and XTAL2 may be used as P4.0 and P4.1 respectively. XTAL2
may also be configured to output a divided version of the system clock. The frequency of the
oscillator may be adjusted within limits by changing the RC Calibration Byte stored at byte 128 of
the User Signature Array. This location may be updated using the IAP interface (location 0180H
in SIG space) or by an external device programmer (UROW location 0080H). See
“User Signature and Analog Configuration” on page
stored at byte 8 of the Atmel Signature Array (0008H in SIG space).
When the AT89LP6440 is configured to use either an external clock or the internal RC oscillator,
the system clock divided by 2 may be output on XTAL2 (P4.1). The clock out feature is enabled
by setting the COE bit in CLKREG. For example, setting COE = “1” when using the internal oscil-
lator will result in a 4.0 MHz (±2.5%) clock output on P4.1. P4.1 must be configured as an output
in order to use the clock out feature.
The CDV
source by powers of 2. The clock divider provides users with a greater frequency range when
using the Internal RC Oscillator. For example, to achieve a 1 MHz system frequency when using
the IRC, CDV
reduce power consumption by decreasing the operational frequency during non-critical periods.
The resulting system frequency is given by the following equation:
where f
for the CPU and all peripherals. The value of CDV may be changed at any time without interrupt-
OSC
2-0
is the frequency of the selected clock source. The clock divider will prescale the clock
bits in CLKREG allow the system clock to be divided down from the selected clock
2-0
External Clock Drive Configuration
should be set to 011B for divide-by-8 operation. The divider can also be used to
OSCILLATOR
NC, GPIO, or
EXTERNAL
CLKOUT
SIGNAL
Figure
f
SYS
AT89LP6440 - Preliminary
=
6-2. XTAL2 may be left unconnected, used as
------------ -
2
f
OSC
CDV
165. A copy of the factory calibration byte is
XTAL2 (P4.1)
XTAL1 (P4.0)
GND
Section 25.8
31