AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 139

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 20-2.
Table 20-3.
Table 20-4.
3706A–MICRO–9/09
Symbol
ADIF
GO/BSY
DAC
ADCE
LADJ
ACK [2-0]
DADC = D9H
Not Bit Addressable
Bit
DADL = DCH
Not Bit Addressable
Bit
DADH = DDH
Not Bit Addressable
Bit
Function
ADC Interrupt Flag. Set by hardware when a conversion completes. Cleared by hardware when calling the interrupt
service routine.
Conversion Start/Busy Flag. In software triggered mode, writing a 1 to this bit starts a conversion. The bit remains high
while the conversion is in progress and is cleared by hardware when the conversion completes. In hardware triggered
mode, this bit is set and cleared by hardware to flag when the DADC is busy.
Digital-to-Analog Conversion Enable. Set to configure the DADC in Digital-to-Analog (DAC) mode. Clear to configure the
DADC in Analog-to-Digital (ADC) mode.
DADC Enable. Set to enable the DADC. Clear to disable the DADC.
Left Adjust Enable. When cleared, the ADC results are right adjusted and the MSBs are sign extended. When set, the
ADC results are left adjusted and the LSBs are zeroed.
DADC Clock Select
ACK3
0
0
0
0
1
1
1
1
DADC
DADL
DADH
ADC.15
ADC.7
ADIF
7
7
7
– DADC Data Low Register
– DADC Control Register
– DADC Data High Register
ACK1
0
0
1
1
0
0
1
1
GO/BSY
ADC.14
ADC.6
6
6
6
ACK0
0
1
0
1
0
1
0
1
ADC.13
ADC.5
DAC
5
Clock Source
Internal RC Oscillator/4 (2MHz)
f
f
f
f
f
f
f
5
5
sys
sys
sys
sys
sys
sys
sys
/2
/4
/8
/16
/32
/64
/128
ADC.12
ADC.4
ADCE
4
4
4
ADC.11
ADC.3
LADJ
3
3
3
AT89LP6440 - Preliminary
ADC.10
ADC.2
ACK2
2
2
2
Reset Value = 0000 0000B
Reset Value = 0000 0000B
Reset Value = 0000 0000B
ADC.1
ADC.9
ACK1
1
1
1
ADC.0
ADC.8
ACK0
0
0
0
139