AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 167
![MCU 8051 64K FLASH ISP 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
AT89LP6440-20AU
Manufacturer Part Number
AT89LP6440-20AU
Description
MCU 8051 64K FLASH ISP 44TQFP
Manufacturer
Atmel
Series
89LPr
Specifications of AT89LP6440-20AU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
8051
Family Name
89LP
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
38
Interface Type
2-Wire/SPI
On-chip Dac
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89LP6440-20AU
Manufacturer:
Cirrus
Quantity:
89
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25.9.4
25.9.5
3706A–MICRO–9/09
ISP Exit Sequence
Serial Peripheral Interface
Figure 25-9. In-System Programming (ISP) Start Sequence
Execute this sequence to exit ISP mode and resume CPU execution mode.
Figure 25-10. In-System Programming (ISP) Exit Sequence
Note:
The Serial Peripheral Interface (SPI) is a byte-oriented full-duplex synchronous serial communi-
cation channel. During In-System Programming, the programmer always acts as the SPI master
and the target device always acts as the SPI slave. The target device receives serial data on
MOSI and outputs serial data on MISO. The Programming Interface implements a standard
SPI Port with a fixed data order and For In-System Programming, bytes are transferred MSB
first as shown in
1. Drive SCK low.
1. Wait at least t
2. Tristate MOSI.
3. Wait at least t
4. Tristate SCK.
5. Wait t
XTAL1
The waveforms on this page are not to scale.
MISO
MOSI
RST
SCK
V
SS
RHZ
DD
XTAL1
MISO
MOSI
RST
SCK
V
SS
DD
and tristate SS.
Figure
SSD
SSZ
and bring RST high.
and drive SS high.
25-11. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0,
t
SSD
t
SSZ
t
t
RLZ
RHZ
AT89LP6440 - Preliminary
HIGH Z
HIGH Z
t
STL
HIGH Z
HIGH Z
t
ZSS
t
SSE
167
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