AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 28

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2.2.2
5.2.2.3
28
AT89LP6440 - Preliminary
Index Disable
Circular Buffers
The MOVC Index Disable bit, MVCD (DSPR.1), disables the indexed addressing mode of the
MOVC A, @A+DPTR instruction. When MVCD = 1, the MOVC instruction functions as
MOVC A, @DPTR with no indexing as shown in
routines that must fetch multiple operands from program memory. DPRB can change the MOVC
destination register from ACC to B, but has no effect on the MOVC index register.
Table 5-7.
The CBE0 and CBE1 bits in DSPR can configure DPTR0 and DPTR1, respectively, to operate in
circular buffer mode. The AT89LP6440 maps circular buffers into two identically sized regions of
EDATA/XDATA. These buffers can speed up convolution computations such as FIR and IAR
digital filters. The length of the buffers are set by the value of the FIRD (E3H) register for up to
256 entries. Buffer A is mapped from 0000H to FIRD and Buffer B is mapped from 0100H to
100H+FIRD as shown in
cular buffer mode is enabled, updates to a data pointer referencing the buffer region will follow
circular addressing rules. If the data pointer is equal to FIRD or 100H+FIRD any increment will
cause it to overflow to 0000H or 0100H respectively. If the data pointer is equal to 0000H or
0100H any decrement will cause it to underflow to FIRD or 100H+FIRD respectively. In this
mode, updates can be either an explicit INC DPTR or an automatic update using DPUn where
the DPDn bits control the direction. The data pointer will increment or decrement normally at any
other addresses. Therefore, when circular addressing is in use, the data pointers can still oper-
ate as regular pointers in the FIRD+1 to 00FFH and greater than 100H+FIRD ranges.
Figure 5-6.
MVCD
0
0
1
1
DPRB
MOVC @DPTR Operating Modes
Circular Buffer Mode
0
1
0
1
A, @A+DPTR0
A, @A+DPTR0
A, @DPTR0
A, @DPTR0
Figure
MOVC
MOVC
MOVC
MOVC
DPTR
5-6. Both data pointers may operate in either buffer. When cir-
DPTR
DPTR
DPS = 0
Equivalent Operation for MOVC A, @A+DPTR
0100h
0000h
A, @A+DPTR1
B, @A+DPTR1
A, @DPTR1
B, @DPTR1
100h + FIRD
/DPTR
MOVC
MOVC
MOVC
MOVC
FIRD
Table
B
A
5-7. MVCD can improve the efficiency of
A, @A+DPTR1
B, @A+DPTR1
A, @DPTR1
B, @DPTR1
MOVC
MOVC
MOVC
MOVC
DPTR
DPS = 1
A, @A+DPTR0
A, @A+DPTR0
A, @DPTR0
A, @DPTR0
3706A–MICRO–9/09
/DPTR
MOVC
MOVC
MOVC
MOVC