AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 159

MCU 8051 64K FLASH ISP 44TQFP

AT89LP6440-20AU

Manufacturer Part Number
AT89LP6440-20AU
Description
MCU 8051 64K FLASH ISP 44TQFP
Manufacturer
Atmel
Series
89LPr
Datasheets

Specifications of AT89LP6440-20AU

Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
8051
Family Name
89LP
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
38
Interface Type
2-Wire/SPI
On-chip Dac
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
AT89LP6440-20AU
Manufacturer:
Cirrus
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AT89LP6440-20AU
Manufacturer:
Atmel
Quantity:
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25.2
3706A–MICRO–9/09
Memory Organization
The AT89LP6440 offers 64K bytes of In-System Programmable (ISP) nonvolatile Flash code
memory and 8K bytes of nonvolatile Flash data memory. In addition, the device contains a 256-
byte User Signature Array and a 128-byte read-only Atmel Signature Array. The memory organi-
zation is shown in
each. A single read or write command may only access half a page (64 bytes) in the memory;
however, write with auto-erase commands will erase an entire 128-byte page even though they
can only write one half page. Each memory type resides in its own address space and is
accessed by commands specific to that memory. However, all memory types share the same
page size.
User configuration fuses are mapped as a row in the memory, with each byte representing one
fuse. From a programming standpoint, fuses are treated the same as normal code bytes except
they are not affected by Chip Erase. Fuses can be enabled at any time by writing 00h to the
appropriate locations in the fuse row. However, to disable a fuse, i.e. set it to FFh, the entire
fuse row must be erased and then reprogrammed. The programmer should read the state of all
the fuses into a temporary location, modify those fuses which need to be disabled, then issue a
Fuse Write with Auto-Erase command using the temporary data. Lock bits are treated in a simi-
lar manner to fuses except they may only be erased (unlocked) by Chip Erase.
Table 25-1.
• The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a
• The AT89LP6440 will enter programming mode only when its reset line (RST) is active (low).
• The RST input may be disabled to gain an extra I/O pin. In these cases the RST pin will
• The SS pin should not be left floating during reset if ISP is enabled.
• The ISP Enable Fuse must be set to allow programming during any reset period. If the ISP
• For standalone programmers, RST may be tied directly to GND to ensure correct entry into
Atmel Signature
User Signature
maximum frequency of 5 MHz.
To simplify this operation, it is recommended that the target reset can be controlled by the In-
System programmer. To avoid problems, the In-System programmer should be able to keep
the entire target system reset for the duration of the programming cycle. The target system
should never attempt to drive the four SPI lines while reset is active.
always function as a reset during power up. To enter programming the RST pin must be
driven low prior to the end of Power-On Reset (POR). After POR has completed the device
will remain in ISP mode until RST is brought high. Once the initial ISP session has ended, the
power to the target device must be cycled OFF and ON to enter another session.
Fuse is disabled, ISP may only be entered at POR.
Programming mode regardless of the device settings.
Memory
CODE
DATA
AT89LP6440 Memory Organization
Table 25-1
65536 bytes
8192 bytes
256 bytes
128 bytes
Capacity
and
Figure
25-3. The memory is divided into pages of 128 bytes
Page Size
128 bytes
128 bytes
128 bytes
128 bytes
AT89LP6440 - Preliminary
# Pages
512
64
2
1
Address Range
0000H – FFFFH
1000H – 3FFFH
0000H – 00FFH
0000H – 007FH
159

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