AT89LP6440-20AU Atmel, AT89LP6440-20AU Datasheet - Page 116

• Manufacturer Part Number: AT89LP6440-20AU
• Description: MCU 8051 64K FLASH ISP 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 38
• Interface Type: 2-Wire/SPI
• On-chip Dac: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
Table 18-6.
116
Status
Code
(TWSR)
0x08
10h
18h
20h
28h
30h
38h
AT89LP6440 - Preliminary
Status of the Two-wire
Serial Bus and Two-wire
Serial Interface Hardware
A START condition has
been transmitted
A repeated START
condition has been
transmitted
SLA+W has been
transmitted; ACK has been
received
SLA+W has been
transmitted; NOT ACK has
been received
Data byte has been
transmitted; ACK has been
received
Data byte has been
transmitted; NOT ACK has
been received
Arbitration lost in SLA+W
or data bytes
Status Codes for Master Transmitter Mode
To/from TWDR
Load SLA+W
Load SLA+W
Load SLA+R
Load data byte
No action
No action
No action
Load data byte
No action
No action
No action
Load data byte
No action
No action
No action
Load data byte
No actio
No actio
No actio
No action
No action
Application Software Response
STA
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
STO
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
To TWCR
TWIF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next Action Taken by TWI Hardware
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted andSTO flag
will be reset
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and STO
flag will be reset
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and STO
flag will be reset
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and STO
flag will be reset
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
Two-wire Serial Bus will be released and not
addressed slave mode entered
A START condition will be transmitted when the
bus becomes free
3706A–MICRO–9/09